From 3cf71b171525b99fab321b73ee7d54e436ef95a9 Mon Sep 17 00:00:00 2001 From: David Mosberger Date: Tue, 19 Aug 2003 09:14:00 -0700 Subject: [PATCH] ia64: Fixes for the inline-asm cleanup patch so the tree builds and works again on the simulator (besides the real hw, of course). Also, clean up simulator bootloader code so it's all in a single place (arch/ia64/hp/sim/bootloader/). --- arch/ia64/Makefile | 2 +- arch/ia64/{ => hp/sim}/boot/Makefile | 0 arch/ia64/hp/sim/boot/boot_head.S | 136 ++++ arch/ia64/{ => hp/sim}/boot/bootloader.c | 0 arch/ia64/{ => hp/sim}/boot/bootloader.lds | 0 arch/ia64/{kernel => hp/sim/boot}/fw-emu.c | 24 +- arch/ia64/hp/sim/boot/ssc.h | 35 + arch/ia64/hp/sim/hpsim.S | 1 - arch/ia64/ia32/ia32_signal.c | 8 +- arch/ia64/ia32/ia32_support.c | 2 +- arch/ia64/ia32/ia32_traps.c | 2 +- arch/ia64/ia32/ia32priv.h | 13 +- arch/ia64/ia32/sys_ia32.c | 4 +- arch/ia64/kernel/irq_ia64.c | 2 +- arch/ia64/kernel/mca.c | 8 +- arch/ia64/kernel/perfmon.c | 25 +- arch/ia64/kernel/setup.c | 4 +- arch/ia64/kernel/signal.c | 11 +- arch/ia64/kernel/traps.c | 4 +- arch/ia64/kernel/unaligned.c | 6 +- include/asm-ia64/bitops.h | 2 +- include/asm-ia64/current.h | 9 +- include/asm-ia64/delay.h | 6 +- include/asm-ia64/gcc_intrin.h | 779 ++++++++++----------- include/asm-ia64/ia64regs.h | 26 +- include/asm-ia64/intrinsics.h | 6 +- include/asm-ia64/io.h | 2 +- include/asm-ia64/page.h | 2 +- include/asm-ia64/processor.h | 31 +- include/asm-ia64/rwsem.h | 9 +- include/asm-ia64/siginfo.h | 1 - include/asm-ia64/smp.h | 2 +- include/asm-ia64/spinlock.h | 6 +- include/asm-ia64/system.h | 28 +- include/asm-ia64/timex.h | 2 +- include/asm-ia64/tlbflush.h | 2 +- include/asm-ia64/unistd.h | 6 +- 37 files changed, 655 insertions(+), 551 deletions(-) rename arch/ia64/{ => hp/sim}/boot/Makefile (100%) create mode 100644 arch/ia64/hp/sim/boot/boot_head.S rename arch/ia64/{ => hp/sim}/boot/bootloader.c (100%) rename arch/ia64/{ => hp/sim}/boot/bootloader.lds (100%) rename arch/ia64/{kernel => hp/sim/boot}/fw-emu.c (95%) create mode 100644 arch/ia64/hp/sim/boot/ssc.h diff --git a/arch/ia64/Makefile b/arch/ia64/Makefile index 2a1b672975972..286291e138604 100644 --- a/arch/ia64/Makefile +++ b/arch/ia64/Makefile @@ -66,7 +66,7 @@ drivers-$(CONFIG_IA64_HP_SIM) += arch/ia64/hp/sim/ drivers-$(CONFIG_IA64_HP_ZX1) += arch/ia64/hp/common/ arch/ia64/hp/zx1/ drivers-$(CONFIG_IA64_GENERIC) += arch/ia64/hp/common/ arch/ia64/hp/zx1/ arch/ia64/hp/sim/ -boot := arch/ia64/boot +boot := arch/ia64/hp/sim/boot .PHONY: boot compressed check diff --git a/arch/ia64/boot/Makefile b/arch/ia64/hp/sim/boot/Makefile similarity index 100% rename from arch/ia64/boot/Makefile rename to arch/ia64/hp/sim/boot/Makefile diff --git a/arch/ia64/hp/sim/boot/boot_head.S b/arch/ia64/hp/sim/boot/boot_head.S new file mode 100644 index 0000000000000..92c20ce3c4049 --- /dev/null +++ b/arch/ia64/hp/sim/boot/boot_head.S @@ -0,0 +1,136 @@ +/* + * Copyright (C) 1998-2003 Hewlett-Packard Co + * David Mosberger-Tang + */ + +#include + + .bss + .align 16 +stack_mem: + .skip 16834 + + .text + +/* This needs to be defined because lib/string.c:strlcat() calls it in case of error... */ +GLOBAL_ENTRY(printk) + break 0 +END(printk) + +GLOBAL_ENTRY(_start) + .prologue + .save rp, r0 + .body + movl gp = __gp + movl sp = stack_mem + bsw.1 + br.call.sptk.many rp=start_bootloader +END(_start) + +GLOBAL_ENTRY(ssc) + .regstk 5,0,0,0 + mov r15=in4 + break 0x80001 + br.ret.sptk.many b0 +END(ssc) + +GLOBAL_ENTRY(jmp_to_kernel) + .regstk 2,0,0,0 + mov r28=in0 + mov b7=in1 + br.sptk.few b7 +END(jmp_to_kernel) + + +GLOBAL_ENTRY(pal_emulator_static) + mov r8=-1 + mov r9=256 + ;; + cmp.gtu p6,p7=r9,r28 /* r28 <= 255? */ +(p6) br.cond.sptk.few static + ;; + mov r9=512 + ;; + cmp.gtu p6,p7=r9,r28 +(p6) br.cond.sptk.few stacked + ;; +static: cmp.eq p6,p7=6,r28 /* PAL_PTCE_INFO */ +(p7) br.cond.sptk.few 1f + ;; + mov r8=0 /* status = 0 */ + movl r9=0x100000000 /* tc.base */ + movl r10=0x0000000200000003 /* count[0], count[1] */ + movl r11=0x1000000000002000 /* stride[0], stride[1] */ + br.cond.sptk.few rp +1: cmp.eq p6,p7=14,r28 /* PAL_FREQ_RATIOS */ +(p7) br.cond.sptk.few 1f + mov r8=0 /* status = 0 */ + movl r9 =0x100000064 /* proc_ratio (1/100) */ + movl r10=0x100000100 /* bus_ratio<<32 (1/256) */ + movl r11=0x100000064 /* itc_ratio<<32 (1/100) */ + ;; +1: cmp.eq p6,p7=19,r28 /* PAL_RSE_INFO */ +(p7) br.cond.sptk.few 1f + mov r8=0 /* status = 0 */ + mov r9=96 /* num phys stacked */ + mov r10=0 /* hints */ + mov r11=0 + br.cond.sptk.few rp +1: cmp.eq p6,p7=1,r28 /* PAL_CACHE_FLUSH */ +(p7) br.cond.sptk.few 1f + mov r9=ar.lc + movl r8=524288 /* flush 512k million cache lines (16MB) */ + ;; + mov ar.lc=r8 + movl r8=0xe000000000000000 + ;; +.loop: fc r8 + add r8=32,r8 + br.cloop.sptk.few .loop + sync.i + ;; + srlz.i + ;; + mov ar.lc=r9 + mov r8=r0 + ;; +1: cmp.eq p6,p7=15,r28 /* PAL_PERF_MON_INFO */ +(p7) br.cond.sptk.few 1f + mov r8=0 /* status = 0 */ + movl r9 =0x12082004 /* generic=4 width=32 retired=8 cycles=18 */ + mov r10=0 /* reserved */ + mov r11=0 /* reserved */ + mov r16=0xffff /* implemented PMC */ + mov r17=0xffff /* implemented PMD */ + add r18=8,r29 /* second index */ + ;; + st8 [r29]=r16,16 /* store implemented PMC */ + st8 [r18]=r0,16 /* clear remaining bits */ + ;; + st8 [r29]=r0,16 /* store implemented PMC */ + st8 [r18]=r0,16 /* clear remaining bits */ + ;; + st8 [r29]=r17,16 /* store implemented PMD */ + st8 [r18]=r0,16 /* clear remaining bits */ + mov r16=0xf0 /* cycles count capable PMC */ + ;; + st8 [r29]=r0,16 /* store implemented PMC */ + st8 [r18]=r0,16 /* clear remaining bits */ + mov r17=0x10 /* retired bundles capable PMC */ + ;; + st8 [r29]=r16,16 /* store cycles capable */ + st8 [r18]=r0,16 /* clear remaining bits */ + ;; + st8 [r29]=r0,16 /* store implemented PMC */ + st8 [r18]=r0,16 /* clear remaining bits */ + ;; + st8 [r29]=r17,16 /* store retired bundle capable */ + st8 [r18]=r0,16 /* clear remaining bits */ + ;; + st8 [r29]=r0,16 /* store implemented PMC */ + st8 [r18]=r0,16 /* clear remaining bits */ + ;; +1: br.cond.sptk.few rp +stacked: + br.ret.sptk.few rp +END(pal_emulator_static) diff --git a/arch/ia64/boot/bootloader.c b/arch/ia64/hp/sim/boot/bootloader.c similarity index 100% rename from arch/ia64/boot/bootloader.c rename to arch/ia64/hp/sim/boot/bootloader.c diff --git a/arch/ia64/boot/bootloader.lds b/arch/ia64/hp/sim/boot/bootloader.lds similarity index 100% rename from arch/ia64/boot/bootloader.lds rename to arch/ia64/hp/sim/boot/bootloader.lds diff --git a/arch/ia64/kernel/fw-emu.c b/arch/ia64/hp/sim/boot/fw-emu.c similarity index 95% rename from arch/ia64/kernel/fw-emu.c rename to arch/ia64/hp/sim/boot/fw-emu.c index cf5702071f28e..95d71afbd2793 100644 --- a/arch/ia64/kernel/fw-emu.c +++ b/arch/ia64/hp/sim/boot/fw-emu.c @@ -3,9 +3,6 @@ * * Copyright (C) 1998-2001 Hewlett-Packard Co * David Mosberger-Tang - * - * For the HP simulator, this file gets include in boot/bootloader.c. - * For SoftSDV, this file gets included in sys_softsdv.c. */ #include @@ -18,6 +15,8 @@ #include #include +#include "ssc.h" + #define MB (1024*1024UL) #define SIMPLE_MEMMAP 1 @@ -37,17 +36,6 @@ static char fw_mem[( sizeof(struct ia64_boot_param) + NUM_MEM_DESCS*(sizeof(efi_memory_desc_t)) + 1024)] __attribute__ ((aligned (8))); -#if defined(CONFIG_IA64_HP_SIM) || defined(CONFIG_IA64_GENERIC) - -/* Simulator system calls: */ - -#define SSC_EXIT 66 - -/* - * Simulator system call. - */ -extern long ssc (long arg0, long arg1, long arg2, long arg3, int nr); - #define SECS_PER_HOUR (60 * 60) #define SECS_PER_DAY (SECS_PER_HOUR * 24) @@ -109,12 +97,6 @@ offtime (unsigned long t, efi_time_t *tp) return 1; } -#endif /* CONFIG_IA64_HP_SIM */ - -/* - * Very ugly, but we need this in the simulator only. Once we run on - * real hw, this can all go away. - */ extern void pal_emulator_static (void); /* Macro to emulate SAL call using legacy IN and OUT calls to CF8, CFC etc.. */ @@ -321,7 +303,7 @@ sys_fw_init (const char *args, int arglen) efi_systab->hdr.headersize = sizeof(efi_systab->hdr); efi_systab->fw_vendor = __pa("H\0e\0w\0l\0e\0t\0t\0-\0P\0a\0c\0k\0a\0r\0d\0\0"); efi_systab->fw_revision = 1; - efi_systab->runtime = __pa(efi_runtime); + efi_systab->runtime = (void *) __pa(efi_runtime); efi_systab->nr_tables = 1; efi_systab->tables = __pa(efi_tables); diff --git a/arch/ia64/hp/sim/boot/ssc.h b/arch/ia64/hp/sim/boot/ssc.h new file mode 100644 index 0000000000000..3b94c03e43a97 --- /dev/null +++ b/arch/ia64/hp/sim/boot/ssc.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 1998-2003 Hewlett-Packard Co + * David Mosberger-Tang + * Stephane Eranian + */ +#ifndef ssc_h +#define ssc_h + +/* Simulator system calls: */ + +#define SSC_CONSOLE_INIT 20 +#define SSC_GETCHAR 21 +#define SSC_PUTCHAR 31 +#define SSC_OPEN 50 +#define SSC_CLOSE 51 +#define SSC_READ 52 +#define SSC_WRITE 53 +#define SSC_GET_COMPLETION 54 +#define SSC_WAIT_COMPLETION 55 +#define SSC_CONNECT_INTERRUPT 58 +#define SSC_GENERATE_INTERRUPT 59 +#define SSC_SET_PERIODIC_INTERRUPT 60 +#define SSC_GET_RTC 65 +#define SSC_EXIT 66 +#define SSC_LOAD_SYMBOLS 69 +#define SSC_GET_TOD 74 + +#define SSC_GET_ARGS 75 + +/* + * Simulator system call. + */ +extern long ssc (long arg0, long arg1, long arg2, long arg3, int nr); + +#endif /* ssc_h */ diff --git a/arch/ia64/hp/sim/hpsim.S b/arch/ia64/hp/sim/hpsim.S index 9c223a3a8b14a..ff16e8a857d12 100644 --- a/arch/ia64/hp/sim/hpsim.S +++ b/arch/ia64/hp/sim/hpsim.S @@ -8,4 +8,3 @@ GLOBAL_ENTRY(ia64_ssc) break 0x80001 br.ret.sptk.many rp END(ia64_ssc) - diff --git a/arch/ia64/ia32/ia32_signal.c b/arch/ia64/ia32/ia32_signal.c index 88e7ca03eabe6..aba19859d2f7d 100644 --- a/arch/ia64/ia32/ia32_signal.c +++ b/arch/ia64/ia32/ia32_signal.c @@ -24,6 +24,7 @@ #include #include +#include #include #include #include @@ -41,8 +42,11 @@ #define __IA32_NR_sigreturn 119 #define __IA32_NR_rt_sigreturn 173 -#include #ifdef ASM_SUPPORTED +/* + * Don't let GCC uses f16-f31 so that save_ia32_fpstate_live() and + * restore_ia32_fpstate_live() can be sure the live register contain user-level state. + */ register double f16 asm ("f16"); register double f17 asm ("f17"); register double f18 asm ("f18"); register double f19 asm ("f19"); register double f20 asm ("f20"); register double f21 asm ("f21"); @@ -217,7 +221,7 @@ save_ia32_fpstate_live (struct _fpstate_ia32 *save) if (!access_ok(VERIFY_WRITE, save, sizeof(*save))) return -EFAULT; - /* Readin fsr, fcr, fir, fdr and copy onto fpstate */ + /* Read in fsr, fcr, fir, fdr and copy onto fpstate */ fsr = ia64_getreg(_IA64_REG_AR_FSR); fcr = ia64_getreg(_IA64_REG_AR_FCR); fir = ia64_getreg(_IA64_REG_AR_FIR); diff --git a/arch/ia64/ia32/ia32_support.c b/arch/ia64/ia32/ia32_support.c index 651e3df7a2c49..4d373270fe3b1 100644 --- a/arch/ia64/ia32/ia32_support.c +++ b/arch/ia64/ia32/ia32_support.c @@ -18,11 +18,11 @@ #include #include +#include #include #include #include #include -#include #include "ia32priv.h" diff --git a/arch/ia64/ia32/ia32_traps.c b/arch/ia64/ia32/ia32_traps.c index 0de400a6b177e..e486042672f10 100644 --- a/arch/ia64/ia32/ia32_traps.c +++ b/arch/ia64/ia32/ia32_traps.c @@ -14,8 +14,8 @@ #include "ia32priv.h" -#include #include +#include int ia32_intercept (struct pt_regs *regs, unsigned long isr) diff --git a/arch/ia64/ia32/ia32priv.h b/arch/ia64/ia32/ia32priv.h index 5f24a94696aaa..50620e5c2d4d9 100644 --- a/arch/ia64/ia32/ia32priv.h +++ b/arch/ia64/ia32/ia32priv.h @@ -446,8 +446,8 @@ extern unsigned long ia32_do_mmap (struct file *, unsigned long, unsigned long, extern void ia32_load_segment_descriptors (struct task_struct *task); #define ia32f2ia64f(dst,src) \ -do { \ - ia64_ldfe(6,src); \ +do { \ + ia64_ldfe(6,src); \ ia64_stop(); \ ia64_stf_spill(dst, 6); \ } while(0) @@ -456,7 +456,7 @@ do { \ do { \ ia64_ldf_fill(6, src); \ ia64_stop(); \ - ia64_stfe(dst, 6); \ + ia64_stfe(dst, 6); \ } while(0) struct user_regs_struct32 { @@ -470,11 +470,8 @@ struct user_regs_struct32 { }; /* Prototypes for use in elfcore32.h */ -int save_ia32_fpstate (struct task_struct *tsk, - struct ia32_user_i387_struct *save); - -int save_ia32_fpxstate (struct task_struct *tsk, - struct ia32_user_fxsr_struct *save); +extern int save_ia32_fpstate (struct task_struct *tsk, struct ia32_user_i387_struct *save); +extern int save_ia32_fpxstate (struct task_struct *tsk, struct ia32_user_fxsr_struct *save); #endif /* !CONFIG_IA32_SUPPORT */ diff --git a/arch/ia64/ia32/sys_ia32.c b/arch/ia64/ia32/sys_ia32.c index d21c4b6e3d16d..10727d0026ffa 100644 --- a/arch/ia64/ia32/sys_ia32.c +++ b/arch/ia64/ia32/sys_ia32.c @@ -51,10 +51,10 @@ #include #include +#include +#include #include #include -#include -#include #include "ia32priv.h" diff --git a/arch/ia64/kernel/irq_ia64.c b/arch/ia64/kernel/irq_ia64.c index fbf529b2147f1..82d4c9891a07b 100644 --- a/arch/ia64/kernel/irq_ia64.c +++ b/arch/ia64/kernel/irq_ia64.c @@ -30,12 +30,12 @@ #include #include +#include #include #include #include #include #include -#include #ifdef CONFIG_PERFMON # include diff --git a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c index 1ad4d10ffe894..3626ec5ef2102 100644 --- a/arch/ia64/kernel/mca.c +++ b/arch/ia64/kernel/mca.c @@ -531,7 +531,7 @@ void ia64_mca_cmc_vector_disable (void *dummy) { cmcv_reg_t cmcv; - + cmcv = (cmcv_reg_t)ia64_getreg(_IA64_REG_CR_CMCV); cmcv.cmcv_mask = 1; /* Mask/disable interrupt */ @@ -558,7 +558,7 @@ void ia64_mca_cmc_vector_enable (void *dummy) { cmcv_reg_t cmcv; - + cmcv = (cmcv_reg_t)ia64_getreg(_IA64_REG_CR_CMCV); cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */ @@ -1146,7 +1146,7 @@ ia64_mca_cmc_int_caller(int cpe_irq, void *arg, struct pt_regs *ptregs) ia64_mca_cmc_int_handler(cpe_irq, arg, ptregs); for (++cpuid ; !cpu_online(cpuid) && cpuid < NR_CPUS ; cpuid++); - + if (cpuid < NR_CPUS) { platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0); } else { @@ -1176,7 +1176,7 @@ ia64_mca_cmc_int_caller(int cpe_irq, void *arg, struct pt_regs *ptregs) start_count = -1; } - + return IRQ_HANDLED; } diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c index a3a2a50916c30..5ed00c1bfe64c 100644 --- a/arch/ia64/kernel/perfmon.c +++ b/arch/ia64/kernel/perfmon.c @@ -39,6 +39,7 @@ #include #include +#include #include #include #include @@ -46,7 +47,6 @@ #include #include #include -#include #ifdef CONFIG_PERFMON /* @@ -680,28 +680,28 @@ static int pfm_end_notify_user(pfm_context_t *ctx); static inline void pfm_clear_psr_pp(void) { - ia64_rsm(IA64_PSR_PP) + ia64_rsm(IA64_PSR_PP); ia64_srlz_i(); } static inline void pfm_set_psr_pp(void) { - ia64_ssm(IA64_PSR_PP) + ia64_ssm(IA64_PSR_PP); ia64_srlz_i(); } static inline void pfm_clear_psr_up(void) { - ia64_rsm(IA64_PSR_UP) + ia64_rsm(IA64_PSR_UP); ia64_srlz_i(); } static inline void pfm_set_psr_up(void) { - ia64_ssm(IA64_PSR_UP) + ia64_ssm(IA64_PSR_UP); ia64_srlz_i(); } @@ -985,8 +985,7 @@ pfm_restore_monitoring(struct task_struct *task) */ if (ctx->ctx_fl_system && (PFM_CPUINFO_GET() & PFM_CPUINFO_DCR_PP)) { /* disable dcr pp */ - ia64_setreg(_IA64_REG_CR_DCR, - ia64_getreg(_IA64_REG_CR_DCR) & ~IA64_DCR_PP); + ia64_setreg(_IA64_REG_CR_DCR, ia64_getreg(_IA64_REG_CR_DCR) & ~IA64_DCR_PP); pfm_clear_psr_pp(); } else { pfm_clear_psr_up(); @@ -1033,8 +1032,7 @@ pfm_restore_monitoring(struct task_struct *task) */ if (ctx->ctx_fl_system && (PFM_CPUINFO_GET() & PFM_CPUINFO_DCR_PP)) { /* enable dcr pp */ - ia64_setreg(_IA64_REG_CR_DCR, - ia64_getreg(_IA64_REG_CR_DCR) | IA64_DCR_PP); + ia64_setreg(_IA64_REG_CR_DCR, ia64_getreg(_IA64_REG_CR_DCR) | IA64_DCR_PP); ia64_srlz_i(); } pfm_set_psr_l(psr); @@ -1790,8 +1788,7 @@ pfm_syswide_force_stop(void *info) /* * Update local PMU */ - ia64_setreg(_IA64_REG_CR_DCR, - ia64_getreg(_IA64_REG_CR_DCR) & ~IA64_DCR_PP); + ia64_setreg(_IA64_REG_CR_DCR, ia64_getreg(_IA64_REG_CR_DCR) & ~IA64_DCR_PP); ia64_srlz_i(); /* * update local cpuinfo @@ -3962,8 +3959,7 @@ pfm_stop(pfm_context_t *ctx, void *arg, int count, struct pt_regs *regs) * * disable dcr pp */ - ia64_setreg(_IA64_REG_CR_DCR, - ia64_getreg(_IA64_REG_CR_DCR) & ~IA64_DCR_PP); + ia64_setreg(_IA64_REG_CR_DCR, ia64_getreg(_IA64_REG_CR_DCR) & ~IA64_DCR_PP); ia64_srlz_i(); /* @@ -4053,8 +4049,7 @@ pfm_start(pfm_context_t *ctx, void *arg, int count, struct pt_regs *regs) pfm_set_psr_pp(); /* enable dcr pp */ - ia64_setreg(_IA64_REG_CR_DCR, - ia64_getreg(_IA64_REG_CR_DCR) | IA64_DCR_PP); + ia64_setreg(_IA64_REG_CR_DCR, ia64_getreg(_IA64_REG_CR_DCR) | IA64_DCR_PP); ia64_srlz_i(); return 0; diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c index 8edc299421d50..c0dd4aa0dba83 100644 --- a/arch/ia64/kernel/setup.c +++ b/arch/ia64/kernel/setup.c @@ -741,8 +741,8 @@ cpu_init (void) * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll * be fine). */ - ia64_setreg(_IA64_REG_CR_DCR, IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX - | IA64_DCR_DR | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC); + ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR + | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); atomic_inc(&init_mm.mm_count); current->active_mm = &init_mm; if (current->mm) diff --git a/arch/ia64/kernel/signal.c b/arch/ia64/kernel/signal.c index 3ecebadd468dd..dd6ba6951f987 100644 --- a/arch/ia64/kernel/signal.c +++ b/arch/ia64/kernel/signal.c @@ -1,7 +1,7 @@ /* * Architecture-specific signal handling support. * - * Copyright (C) 1999-2002 Hewlett-Packard Co + * Copyright (C) 1999-2003 Hewlett-Packard Co * David Mosberger-Tang * * Derived from i386 and Alpha versions. @@ -23,6 +23,7 @@ #include #include +#include #include #include #include @@ -41,8 +42,12 @@ # define GET_SIGSET(k,u) __get_user((k)->sig[0], &(u)->sig[0]) #endif -#include #ifdef ASM_SUPPORTED +/* + * Don't let GCC uses f16-f31 so that when we setup/restore the registers in the signal + * context in __kernel_sigtramp(), we can be sure that registers f16-f31 contain user-level + * values. + */ register double f16 asm ("f16"); register double f17 asm ("f17"); register double f18 asm ("f18"); register double f19 asm ("f19"); register double f20 asm ("f20"); register double f21 asm ("f21"); @@ -195,7 +200,7 @@ copy_siginfo_to_user (siginfo_t *to, siginfo_t *from) case __SI_TIMER >> 16: err |= __put_user(from->si_tid, &to->si_tid); err |= __put_user(from->si_overrun, &to->si_overrun); - err |= __put_user(from->si_value.sival_ptr, &to->si_value.sival_ptr); + err |= __put_user(from->si_ptr, &to->si_ptr); break; case __SI_CHLD >> 16: err |= __put_user(from->si_utime, &to->si_utime); diff --git a/arch/ia64/kernel/traps.c b/arch/ia64/kernel/traps.c index fdb43f8186a84..ddd4cb1a25a71 100644 --- a/arch/ia64/kernel/traps.c +++ b/arch/ia64/kernel/traps.c @@ -14,12 +14,13 @@ #include #include /* For unblank_screen() */ +#include #include #include +#include #include #include -#include /* * fp_emulate() needs to be able to access and update all floating point registers. Those * saved in pt_regs can be accessed through that structure, but those not saved, will be @@ -28,7 +29,6 @@ * by declaring preserved registers that are not marked as "fixed" as global register * variables. */ -#include #ifdef ASM_SUPPORTED register double f2 asm ("f2"); register double f3 asm ("f3"); register double f4 asm ("f4"); register double f5 asm ("f5"); diff --git a/arch/ia64/kernel/unaligned.c b/arch/ia64/kernel/unaligned.c index 06595d8d37dbc..95f77b1dfa117 100644 --- a/arch/ia64/kernel/unaligned.c +++ b/arch/ia64/kernel/unaligned.c @@ -18,11 +18,11 @@ #include #include -#include -#include +#include #include +#include +#include #include -#include extern void die_if_kernel(char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn)); diff --git a/include/asm-ia64/bitops.h b/include/asm-ia64/bitops.h index 2a4b667058d9e..295ff0aa820b1 100644 --- a/include/asm-ia64/bitops.h +++ b/include/asm-ia64/bitops.h @@ -292,7 +292,7 @@ ffz (unsigned long x) { unsigned long result; - result = ia64_popcnt((x & (~x - 1))); + result = ia64_popcnt(x & (~x - 1)); return result; } diff --git a/include/asm-ia64/current.h b/include/asm-ia64/current.h index f8b27b5b8fa8b..8e316f179815d 100644 --- a/include/asm-ia64/current.h +++ b/include/asm-ia64/current.h @@ -7,8 +7,11 @@ */ #include -/* In kernel mode, thread pointer (r13) is used to point to the - current task structure. */ -#define current ((struct task_struct *) ia64_getreg(_IA64_REG_TP)) + +/* + * In kernel mode, thread pointer (r13) is used to point to the current task + * structure. + */ +#define current ((struct task_struct *) ia64_getreg(_IA64_REG_TP)) #endif /* _ASM_IA64_CURRENT_H */ diff --git a/include/asm-ia64/delay.h b/include/asm-ia64/delay.h index 1725d43e74bac..74c542acc1e8a 100644 --- a/include/asm-ia64/delay.h +++ b/include/asm-ia64/delay.h @@ -5,7 +5,7 @@ * Delay routines using a pre-computed "cycles/usec" value. * * Copyright (C) 1998, 1999 Hewlett-Packard Co - * Copyright (C) 1998, 1999 David Mosberger-Tang + * David Mosberger-Tang * Copyright (C) 1999 VA Linux Systems * Copyright (C) 1999 Walt Drummond * Copyright (C) 1999 Asit Mallick @@ -17,8 +17,8 @@ #include #include -#include #include +#include static __inline__ void ia64_set_itm (unsigned long val) @@ -73,7 +73,7 @@ __delay (unsigned long loops) if (loops < 1) return; - for (;loops--;) + while (loops--) ia64_nop(0); } diff --git a/include/asm-ia64/gcc_intrin.h b/include/asm-ia64/gcc_intrin.h index 41a24523d953b..5175f0345555c 100644 --- a/include/asm-ia64/gcc_intrin.h +++ b/include/asm-ia64/gcc_intrin.h @@ -12,89 +12,86 @@ /* Optimization barrier */ /* The "volatile" is due to gcc bugs */ -#define ia64_barrier() __asm__ __volatile__ ("":::"memory") - - -#define ia64_stop() __asm__ __volatile__ (";;"::) - - -#define ia64_invala_gr(regnum) \ - __asm__ __volatile__ ("invala.e r%0" :: "i"(regnum)) - -#define ia64_invala_fr(regnum) \ - __asm__ __volatile__ ("invala.e f%0" :: "i"(regnum)) - -extern void ia64_bad_param_for_setreg(void); -extern void ia64_bad_param_for_getreg(void); - -#define ia64_setreg(regnum, val) \ -({ \ - switch (regnum) { \ - case _IA64_REG_PSR_L: \ - __asm__ __volatile__ ("mov psr.l=%0" :: "r"(val) : "memory"); \ - break; \ - case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC: \ - __asm__ __volatile__ ("mov ar%0=%1" :: \ - "i" (regnum - _IA64_REG_AR_KR0), \ - "r"(val): "memory"); \ - break; \ - case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1: \ - __asm__ __volatile__ ("mov cr%0=%1" :: \ - "i" (regnum - _IA64_REG_CR_DCR), \ - "r"(val): "memory" ); \ - break; \ - case _IA64_REG_SP: \ - __asm__ __volatile__ ("mov r12=%0" :: \ - "r"(val): "memory"); \ - break; \ - case _IA64_REG_GP: \ - __asm__ __volatile__ ("mov gp=%0" :: "r"(val) : "memory"); \ - break; \ - default: \ - ia64_bad_param_for_setreg(); \ - break; \ - } \ -}) - -#define ia64_getreg(regnum) \ -({ \ - __u64 ia64_intri_res; \ - \ - switch (regnum) { \ - case _IA64_REG_GP: \ - __asm__ __volatile__ ("mov %0=gp" : "=r"(ia64_intri_res)); \ - break; \ - case _IA64_REG_IP: \ - __asm__ __volatile__ ("mov %0=ip" : "=r"(ia64_intri_res)); \ - break; \ - case _IA64_REG_PSR: \ - __asm__ __volatile__ ("mov %0=psr" : "=r"(ia64_intri_res));\ - break; \ - case _IA64_REG_TP: /* for current() */ \ - { \ - register __u64 ia64_r13 asm ("r13"); \ - ia64_intri_res = ia64_r13; \ - } \ - break; \ - case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC: \ - __asm__ __volatile__ ("mov %0=ar%1" : "=r" (ia64_intri_res) \ - : "i"(regnum - _IA64_REG_AR_KR0)); \ - break; \ - case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1: \ - __asm__ __volatile__ ("mov %0=cr%1" : "=r" (ia64_intri_res) \ - : "i" (regnum - _IA64_REG_CR_DCR)); \ - break; \ - case _IA64_REG_SP: \ - __asm__ __volatile__ ("mov %0=sp" : "=r" (ia64_intri_res)); \ - break; \ - default: \ - ia64_bad_param_for_getreg(); \ - break; \ - } \ - ia64_intri_res; \ +#define ia64_barrier() asm volatile ("":::"memory") + +#define ia64_stop() asm volatile (";;"::) + +#define ia64_invala_gr(regnum) asm volatile ("invala.e r%0" :: "i"(regnum)) + +#define ia64_invala_fr(regnum) asm volatile ("invala.e f%0" :: "i"(regnum)) + +extern void ia64_bad_param_for_setreg (void); +extern void ia64_bad_param_for_getreg (void); + +#define ia64_setreg(regnum, val) \ +({ \ + switch (regnum) { \ + case _IA64_REG_PSR_L: \ + asm volatile ("mov psr.l=%0" :: "r"(val) : "memory"); \ + break; \ + case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC: \ + asm volatile ("mov ar%0=%1" :: \ + "i" (regnum - _IA64_REG_AR_KR0), \ + "r"(val): "memory"); \ + break; \ + case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1: \ + asm volatile ("mov cr%0=%1" :: \ + "i" (regnum - _IA64_REG_CR_DCR), \ + "r"(val): "memory" ); \ + break; \ + case _IA64_REG_SP: \ + asm volatile ("mov r12=%0" :: \ + "r"(val): "memory"); \ + break; \ + case _IA64_REG_GP: \ + asm volatile ("mov gp=%0" :: "r"(val) : "memory"); \ + break; \ + default: \ + ia64_bad_param_for_setreg(); \ + break; \ + } \ +}) + +#define ia64_getreg(regnum) \ +({ \ + __u64 ia64_intri_res; \ + \ + switch (regnum) { \ + case _IA64_REG_GP: \ + asm volatile ("mov %0=gp" : "=r"(ia64_intri_res)); \ + break; \ + case _IA64_REG_IP: \ + asm volatile ("mov %0=ip" : "=r"(ia64_intri_res)); \ + break; \ + case _IA64_REG_PSR: \ + asm volatile ("mov %0=psr" : "=r"(ia64_intri_res)); \ + break; \ + case _IA64_REG_TP: /* for current() */ \ + { \ + register __u64 ia64_r13 asm ("r13"); \ + ia64_intri_res = ia64_r13; \ + } \ + break; \ + case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC: \ + asm volatile ("mov %0=ar%1" : "=r" (ia64_intri_res) \ + : "i"(regnum - _IA64_REG_AR_KR0)); \ + break; \ + case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1: \ + asm volatile ("mov %0=cr%1" : "=r" (ia64_intri_res) \ + : "i" (regnum - _IA64_REG_CR_DCR)); \ + break; \ + case _IA64_REG_SP: \ + asm volatile ("mov %0=sp" : "=r" (ia64_intri_res)); \ + break; \ + default: \ + ia64_bad_param_for_getreg(); \ + break; \ + } \ + ia64_intri_res; \ }) #define ia64_hint_pause 0 + #define ia64_hint(mode) \ ({ \ switch (mode) { \ @@ -112,434 +109,389 @@ extern void ia64_bad_param_for_getreg(void); #define ia64_mux1_alt 10 #define ia64_mux1_rev 11 -#define ia64_mux1(x, mode) \ -({ \ - __u64 ia64_intri_res; \ - \ - switch (mode) { \ - case ia64_mux1_brcst: \ - __asm__ ("mux1 %0=%1,@brcst" : "=r" (ia64_intri_res) : "r" (x)); \ - break; \ - case ia64_mux1_mix: \ - __asm__ ("mux1 %0=%1,@mix" : "=r" (ia64_intri_res) : "r" (x)); \ - break; \ - case ia64_mux1_shuf: \ - __asm__ ("mux1 %0=%1,@shuf" : "=r" (ia64_intri_res) : "r" (x)); \ - break; \ - case ia64_mux1_alt: \ - __asm__ ("mux1 %0=%1,@alt" : "=r" (ia64_intri_res) : "r" (x)); \ - break; \ - case ia64_mux1_rev: \ - __asm__ ("mux1 %0=%1,@rev" : "=r" (ia64_intri_res) : "r" (x)); \ - break; \ - } \ - ia64_intri_res; \ +#define ia64_mux1(x, mode) \ +({ \ + __u64 ia64_intri_res; \ + \ + switch (mode) { \ + case ia64_mux1_brcst: \ + asm ("mux1 %0=%1,@brcst" : "=r" (ia64_intri_res) : "r" (x)); \ + break; \ + case ia64_mux1_mix: \ + asm ("mux1 %0=%1,@mix" : "=r" (ia64_intri_res) : "r" (x)); \ + break; \ + case ia64_mux1_shuf: \ + asm ("mux1 %0=%1,@shuf" : "=r" (ia64_intri_res) : "r" (x)); \ + break; \ + case ia64_mux1_alt: \ + asm ("mux1 %0=%1,@alt" : "=r" (ia64_intri_res) : "r" (x)); \ + break; \ + case ia64_mux1_rev: \ + asm ("mux1 %0=%1,@rev" : "=r" (ia64_intri_res) : "r" (x)); \ + break; \ + } \ + ia64_intri_res; \ }) - #define ia64_popcnt(x) \ ({ \ __u64 ia64_intri_res; \ - __asm__ ("popcnt %0=%1" : "=r" (ia64_intri_res) : "r" (x)); \ + asm ("popcnt %0=%1" : "=r" (ia64_intri_res) : "r" (x)); \ \ ia64_intri_res; \ }) - #define ia64_getf_exp(x) \ ({ \ long ia64_intri_res; \ \ - __asm__ ("getf.exp %0=%1" : "=r"(ia64_intri_res) : "f"(x)); \ + asm ("getf.exp %0=%1" : "=r"(ia64_intri_res) : "f"(x)); \ \ ia64_intri_res; \ }) -#define ia64_shrp(a, b, count) \ -({ \ - __u64 ia64_intri_res; \ - __asm__ ("shrp %0=%1,%2,%3" : "=r"(ia64_intri_res) : "r"(a), "r"(b), "i"(count)); \ - ia64_intri_res; \ +#define ia64_shrp(a, b, count) \ +({ \ + __u64 ia64_intri_res; \ + asm ("shrp %0=%1,%2,%3" : "=r"(ia64_intri_res) : "r"(a), "r"(b), "i"(count)); \ + ia64_intri_res; \ }) - #define ia64_ldfs(regnum, x) \ ({ \ register double __f__ asm ("f"#regnum); \ - __asm__ __volatile__ ("ldfs %0=[%1]" :"=f"(__f__): "r"(x)); \ + asm volatile ("ldfs %0=[%1]" :"=f"(__f__): "r"(x)); \ }) #define ia64_ldfd(regnum, x) \ ({ \ register double __f__ asm ("f"#regnum); \ - __asm__ __volatile__ ("ldfd %0=[%1]" :"=f"(__f__): "r"(x)); \ + asm volatile ("ldfd %0=[%1]" :"=f"(__f__): "r"(x)); \ }) #define ia64_ldfe(regnum, x) \ ({ \ register double __f__ asm ("f"#regnum); \ - __asm__ __volatile__ ("ldfe %0=[%1]" :"=f"(__f__): "r"(x)); \ + asm volatile ("ldfe %0=[%1]" :"=f"(__f__): "r"(x)); \ }) #define ia64_ldf8(regnum, x) \ ({ \ register double __f__ asm ("f"#regnum); \ - __asm__ __volatile__ ("ldf8 %0=[%1]" :"=f"(__f__): "r"(x)); \ + asm volatile ("ldf8 %0=[%1]" :"=f"(__f__): "r"(x)); \ }) #define ia64_ldf_fill(regnum, x) \ ({ \ register double __f__ asm ("f"#regnum); \ - __asm__ __volatile__ ("ldf.fill %0=[%1]" :"=f"(__f__): "r"(x)); \ -}) - -#define ia64_stfs(x, regnum) \ -({ \ - register double __f__ asm ("f"#regnum); \ - __asm__ __volatile__ ("stfs [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \ -}) - - -#define ia64_stfd(x, regnum) \ -({ \ - register double __f__ asm ("f"#regnum); \ - __asm__ __volatile__ ("stfd [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \ + asm volatile ("ldf.fill %0=[%1]" :"=f"(__f__): "r"(x)); \ }) -#define ia64_stfe(x, regnum) \ -({ \ - register double __f__ asm ("f"#regnum); \ - __asm__ __volatile__ ("stfe [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \ +#define ia64_stfs(x, regnum) \ +({ \ + register double __f__ asm ("f"#regnum); \ + asm volatile ("stfs [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \ }) - -#define ia64_stf8(x, regnum) \ -({ \ - register double __f__ asm ("f"#regnum); \ - __asm__ __volatile__ ("stf8 [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \ +#define ia64_stfd(x, regnum) \ +({ \ + register double __f__ asm ("f"#regnum); \ + asm volatile ("stfd [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \ }) -#define ia64_stf_spill(x, regnum) \ -({ \ - register double __f__ asm ("f"#regnum); \ - __asm__ __volatile__ ("stf.spill [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \ +#define ia64_stfe(x, regnum) \ +({ \ + register double __f__ asm ("f"#regnum); \ + asm volatile ("stfe [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \ }) -#define ia64_fetchadd4_acq(p, inc) \ +#define ia64_stf8(x, regnum) \ +({ \ + register double __f__ asm ("f"#regnum); \ + asm volatile ("stf8 [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \ +}) + +#define ia64_stf_spill(x, regnum) \ +({ \ + register double __f__ asm ("f"#regnum); \ + asm volatile ("stf.spill [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \ +}) + +#define ia64_fetchadd4_acq(p, inc) \ +({ \ + \ + __u64 ia64_intri_res; \ + asm volatile ("fetchadd4.acq %0=[%1],%2" \ + : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \ + : "memory"); \ + \ + ia64_intri_res; \ +}) + +#define ia64_fetchadd4_rel(p, inc) \ +({ \ + __u64 ia64_intri_res; \ + asm volatile ("fetchadd4.rel %0=[%1],%2" \ + : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \ + : "memory"); \ + \ + ia64_intri_res; \ +}) + +#define ia64_fetchadd8_acq(p, inc) \ +({ \ + \ + __u64 ia64_intri_res; \ + asm volatile ("fetchadd8.acq %0=[%1],%2" \ + : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \ + : "memory"); \ + \ + ia64_intri_res; \ +}) + +#define ia64_fetchadd8_rel(p, inc) \ +({ \ + __u64 ia64_intri_res; \ + asm volatile ("fetchadd8.rel %0=[%1],%2" \ + : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \ + : "memory"); \ + \ + ia64_intri_res; \ +}) + +#define ia64_xchg1(ptr,x) \ ({ \ - \ __u64 ia64_intri_res; \ - __asm__ __volatile__ ("fetchadd4.acq %0=[%1],%2" \ - : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \ - : "memory"); \ - \ + asm __volatile ("xchg1 %0=[%1],%2" : "=r" (ia64_intri_res) \ + : "r" (ptr), "r" (x) : "memory"); \ ia64_intri_res; \ }) -#define ia64_fetchadd4_rel(p, inc) \ +#define ia64_xchg2(ptr,x) \ ({ \ __u64 ia64_intri_res; \ - __asm__ __volatile__ ("fetchadd4.rel %0=[%1],%2" \ - : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \ - : "memory"); \ - \ + asm __volatile ("xchg2 %0=[%1],%2" : "=r" (ia64_intri_res) \ + : "r" (ptr), "r" (x) : "memory"); \ ia64_intri_res; \ }) - -#define ia64_fetchadd8_acq(p, inc) \ +#define ia64_xchg4(ptr,x) \ ({ \ - \ __u64 ia64_intri_res; \ - __asm__ __volatile__ ("fetchadd8.acq %0=[%1],%2" \ - : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \ - : "memory"); \ - \ + asm __volatile ("xchg4 %0=[%1],%2" : "=r" (ia64_intri_res) \ + : "r" (ptr), "r" (x) : "memory"); \ ia64_intri_res; \ }) -#define ia64_fetchadd8_rel(p, inc) \ +#define ia64_xchg8(ptr,x) \ ({ \ __u64 ia64_intri_res; \ - __asm__ __volatile__ ("fetchadd8.rel %0=[%1],%2" \ - : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \ - : "memory"); \ - \ + asm __volatile ("xchg8 %0=[%1],%2" : "=r" (ia64_intri_res) \ + : "r" (ptr), "r" (x) : "memory"); \ ia64_intri_res; \ }) - -#define ia64_xchg1(ptr,x) \ -({ \ - __u64 ia64_intri_res; \ - __asm__ __volatile ("xchg1 %0=[%1],%2" : "=r" (ia64_intri_res) \ - : "r" (ptr), "r" (x) : "memory"); \ - ia64_intri_res; \ +#define ia64_cmpxchg1_acq(ptr, new, old) \ +({ \ + __u64 ia64_intri_res; \ + asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ + asm volatile ("cmpxchg1.acq %0=[%1],%2,ar.ccv": \ + "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ + ia64_intri_res; \ }) -#define ia64_xchg2(ptr,x) \ -({ \ - __u64 ia64_intri_res; \ - __asm__ __volatile ("xchg2 %0=[%1],%2" : "=r" (ia64_intri_res) \ - : "r" (ptr), "r" (x) : "memory"); \ - ia64_intri_res; \ +#define ia64_cmpxchg1_rel(ptr, new, old) \ +({ \ + __u64 ia64_intri_res; \ + asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ + asm volatile ("cmpxchg1.rel %0=[%1],%2,ar.ccv": \ + "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ + ia64_intri_res; \ }) -#define ia64_xchg4(ptr,x) \ -({ \ - __u64 ia64_intri_res; \ - __asm__ __volatile ("xchg4 %0=[%1],%2" : "=r" (ia64_intri_res) \ - : "r" (ptr), "r" (x) : "memory"); \ - ia64_intri_res; \ +#define ia64_cmpxchg2_acq(ptr, new, old) \ +({ \ + __u64 ia64_intri_res; \ + asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ + asm volatile ("cmpxchg2.acq %0=[%1],%2,ar.ccv": \ + "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ + ia64_intri_res; \ }) -#define ia64_xchg8(ptr,x) \ -({ \ - __u64 ia64_intri_res; \ - __asm__ __volatile ("xchg8 %0=[%1],%2" : "=r" (ia64_intri_res) \ - : "r" (ptr), "r" (x) : "memory"); \ - ia64_intri_res; \ -}) - -#define ia64_cmpxchg1_acq(ptr, new, old) \ -({ \ - __u64 ia64_intri_res; \ - __asm__ __volatile__ ("mov ar.ccv=%0;;" :: "rO"(old)); \ - __asm__ __volatile__ ("cmpxchg1.acq %0=[%1],%2,ar.ccv": \ - "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ - ia64_intri_res; \ -}) - -#define ia64_cmpxchg1_rel(ptr, new, old) \ -({ \ - __u64 ia64_intri_res; \ - __asm__ __volatile__ ("mov ar.ccv=%0;;" :: "rO"(old)); \ - __asm__ __volatile__ ("cmpxchg1.rel %0=[%1],%2,ar.ccv": \ - "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ - ia64_intri_res; \ +#define ia64_cmpxchg2_rel(ptr, new, old) \ +({ \ + __u64 ia64_intri_res; \ + asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ + \ + asm volatile ("cmpxchg2.rel %0=[%1],%2,ar.ccv": \ + "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ + ia64_intri_res; \ }) -#define ia64_cmpxchg2_acq(ptr, new, old) \ -({ \ - __u64 ia64_intri_res; \ - __asm__ __volatile__ ("mov ar.ccv=%0;;" :: "rO"(old)); \ - __asm__ __volatile__ ("cmpxchg2.acq %0=[%1],%2,ar.ccv": \ - "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ - ia64_intri_res; \ +#define ia64_cmpxchg4_acq(ptr, new, old) \ +({ \ + __u64 ia64_intri_res; \ + asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ + asm volatile ("cmpxchg4.acq %0=[%1],%2,ar.ccv": \ + "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ + ia64_intri_res; \ }) -#define ia64_cmpxchg2_rel(ptr, new, old) \ -({ \ - __u64 ia64_intri_res; \ - __asm__ __volatile__ ("mov ar.ccv=%0;;" :: "rO"(old)); \ - \ - __asm__ __volatile__ ("cmpxchg2.rel %0=[%1],%2,ar.ccv": \ - "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ - ia64_intri_res; \ +#define ia64_cmpxchg4_rel(ptr, new, old) \ +({ \ + __u64 ia64_intri_res; \ + asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ + asm volatile ("cmpxchg4.rel %0=[%1],%2,ar.ccv": \ + "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ + ia64_intri_res; \ }) -#define ia64_cmpxchg4_acq(ptr, new, old) \ -({ \ - __u64 ia64_intri_res; \ - __asm__ __volatile__ ("mov ar.ccv=%0;;" :: "rO"(old)); \ - __asm__ __volatile__ ("cmpxchg4.acq %0=[%1],%2,ar.ccv": \ - "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ - ia64_intri_res; \ +#define ia64_cmpxchg8_acq(ptr, new, old) \ +({ \ + __u64 ia64_intri_res; \ + asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ + asm volatile ("cmpxchg8.acq %0=[%1],%2,ar.ccv": \ + "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ + ia64_intri_res; \ }) -#define ia64_cmpxchg4_rel(ptr, new, old) \ -({ \ - __u64 ia64_intri_res; \ - __asm__ __volatile__ ("mov ar.ccv=%0;;" :: "rO"(old)); \ - __asm__ __volatile__ ("cmpxchg4.rel %0=[%1],%2,ar.ccv": \ - "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ - ia64_intri_res; \ +#define ia64_cmpxchg8_rel(ptr, new, old) \ +({ \ + __u64 ia64_intri_res; \ + asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ + \ + asm volatile ("cmpxchg8.rel %0=[%1],%2,ar.ccv": \ + "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ + ia64_intri_res; \ }) -#define ia64_cmpxchg8_acq(ptr, new, old) \ -({ \ - __u64 ia64_intri_res; \ - __asm__ __volatile__ ("mov ar.ccv=%0;;" :: "rO"(old)); \ - __asm__ __volatile__ ("cmpxchg8.acq %0=[%1],%2,ar.ccv": \ - "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ - ia64_intri_res; \ -}) - -#define ia64_cmpxchg8_rel(ptr, new, old) \ -({ \ - __u64 ia64_intri_res; \ - __asm__ __volatile__ ("mov ar.ccv=%0;;" :: "rO"(old)); \ - \ - __asm__ __volatile__ ("cmpxchg8.rel %0=[%1],%2,ar.ccv": \ - "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \ - ia64_intri_res; \ -}) +#define ia64_mf() asm volatile ("mf" ::: "memory") +#define ia64_mfa() asm volatile ("mf.a" ::: "memory") -#define ia64_mf() __asm__ __volatile__ ("mf" ::: "memory") -#define ia64_mfa() __asm__ __volatile__ ("mf.a" ::: "memory") +#define ia64_invala() asm volatile ("invala" ::: "memory") - -#define ia64_invala() __asm__ __volatile__ ("invala" ::: "memory") - -#define ia64_thash(addr) \ -({ \ - __u64 ia64_intri_res; \ - __asm__ __volatile__ ("thash %0=%1" : "=r"(ia64_intri_res) : "r" (addr)); \ - ia64_intri_res; \ +#define ia64_thash(addr) \ +({ \ + __u64 ia64_intri_res; \ + asm volatile ("thash %0=%1" : "=r"(ia64_intri_res) : "r" (addr)); \ + ia64_intri_res; \ }) +#define ia64_srlz_i() asm volatile (";; srlz.i ;;" ::: "memory") -#define ia64_srlz_i() __asm__ __volatile__ (";; srlz.i ;;" ::: "memory") - +#define ia64_srlz_d() asm volatile (";; srlz.d" ::: "memory"); -#define ia64_srlz_d() __asm__ __volatile__ (";; srlz.d" ::: "memory"); +#define ia64_nop(x) asm volatile ("nop %0"::"i"(x)); +#define ia64_itci(addr) asm volatile ("itc.i %0;;" :: "r"(addr) : "memory") -#define ia64_nop(x) __asm__ __volatile__ ("nop %0"::"i"(x)); +#define ia64_itcd(addr) asm volatile ("itc.d %0;;" :: "r"(addr) : "memory") -#define ia64_itci(addr) __asm__ __volatile__ ("itc.i %0;;" :: "r"(addr) : "memory") +#define ia64_itri(trnum, addr) asm volatile ("itr.i itr[%0]=%1" \ + :: "r"(trnum), "r"(addr) : "memory") -#define ia64_itcd(addr) __asm__ __volatile__ ("itc.d %0;;" :: "r"(addr) : "memory") +#define ia64_itrd(trnum, addr) asm volatile ("itr.d dtr[%0]=%1" \ + :: "r"(trnum), "r"(addr) : "memory") - -#define ia64_itri(trnum, addr) __asm__ __volatile__ ("itr.i itr[%0]=%1" \ - :: "r"(trnum), "r"(addr) : "memory") - - -#define ia64_itrd(trnum, addr) __asm__ __volatile__ ("itr.d dtr[%0]=%1" \ - :: "r"(trnum), "r"(addr) : "memory") - - -#define ia64_tpa(addr) \ -({ \ - __u64 ia64_pa; \ - __asm__ __volatile__ ("tpa %0 = %1" : "=r"(ia64_pa) : "r"(addr) : \ - "memory"); \ +#define ia64_tpa(addr) \ +({ \ + __u64 ia64_pa; \ + asm volatile ("tpa %0 = %1" : "=r"(ia64_pa) : "r"(addr) : "memory"); \ ia64_pa; \ }) -#define __ia64_set_dbr(index, val) \ - __asm__ __volatile__ ("mov dbr[%0]=%1" :: "r"(index), "r"(val) \ - : "memory") +#define __ia64_set_dbr(index, val) \ + asm volatile ("mov dbr[%0]=%1" :: "r"(index), "r"(val) : "memory") -#define ia64_set_ibr(index, val) \ - __asm__ __volatile__ ("mov ibr[%0]=%1" :: "r"(index), "r"(val) \ - : "memory") +#define ia64_set_ibr(index, val) \ + asm volatile ("mov ibr[%0]=%1" :: "r"(index), "r"(val) : "memory") -#define ia64_set_pkr(index, val) \ - __asm__ __volatile__ ("mov pkr[%0]=%1" :: "r"(index), "r"(val) \ - : "memory") +#define ia64_set_pkr(index, val) \ + asm volatile ("mov pkr[%0]=%1" :: "r"(index), "r"(val) : "memory") -#define ia64_set_pmc(index, val) \ - __asm__ __volatile__ ("mov pmc[%0]=%1" :: "r"(index), "r"(val) \ - : "memory"); +#define ia64_set_pmc(index, val) \ + asm volatile ("mov pmc[%0]=%1" :: "r"(index), "r"(val) : "memory") -#define ia64_set_pmd(index, val) \ - __asm__ __volatile__ ("mov pmd[%0]=%1" :: "r"(index), "r"(val) \ - : "memory"); +#define ia64_set_pmd(index, val) \ + asm volatile ("mov pmd[%0]=%1" :: "r"(index), "r"(val) : "memory") -#define ia64_set_rr(index, val) \ - __asm__ __volatile__ ("mov rr[%0]=%1" :: "r"(index), "r"(val) \ - : "memory"); +#define ia64_set_rr(index, val) \ + asm volatile ("mov rr[%0]=%1" :: "r"(index), "r"(val) : "memory"); - -#define ia64_get_cpuid(index) \ -({ \ - __u64 ia64_intri_res; \ - \ - __asm__ __volatile__ ("mov %0=cpuid[%r1]" : "=r"(ia64_intri_res) : "rO"(index)); \ - \ - ia64_intri_res; \ +#define ia64_get_cpuid(index) \ +({ \ + __u64 ia64_intri_res; \ + asm volatile ("mov %0=cpuid[%r1]" : "=r"(ia64_intri_res) : "rO"(index)); \ + ia64_intri_res; \ }) -#define __ia64_get_dbr(index) \ -({ \ - __u64 ia64_intri_res; \ - \ - __asm__ __volatile__ ("mov %0=dbr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ - \ - ia64_intri_res; \ +#define __ia64_get_dbr(index) \ +({ \ + __u64 ia64_intri_res; \ + asm volatile ("mov %0=dbr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ + ia64_intri_res; \ }) -#define ia64_get_ibr(index) \ -({ \ - __u64 ia64_intri_res; \ - \ - __asm__ __volatile__ ("mov %0=ibr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ - \ - ia64_intri_res; \ +#define ia64_get_ibr(index) \ +({ \ + __u64 ia64_intri_res; \ + asm volatile ("mov %0=ibr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ + ia64_intri_res; \ }) -#define ia64_get_pkr(index) \ -({ \ - __u64 ia64_intri_res; \ - \ - __asm__ __volatile__ ("mov %0=pkr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ - \ - ia64_intri_res; \ +#define ia64_get_pkr(index) \ +({ \ + __u64 ia64_intri_res; \ + asm volatile ("mov %0=pkr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ + ia64_intri_res; \ }) -#define ia64_get_pmc(index) \ -({ \ - __u64 ia64_intri_res; \ - \ - __asm__ __volatile__ ("mov %0=pmc[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ - \ - ia64_intri_res; \ +#define ia64_get_pmc(index) \ +({ \ + __u64 ia64_intri_res; \ + asm volatile ("mov %0=pmc[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ + ia64_intri_res; \ }) -#define ia64_get_pmd(index) \ -({ \ - __u64 ia64_intri_res; \ - \ - __asm__ __volatile__ ("mov %0=pmd[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ - \ - ia64_intri_res; \ +#define ia64_get_pmd(index) \ +({ \ + __u64 ia64_intri_res; \ + asm volatile ("mov %0=pmd[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ + ia64_intri_res; \ }) -#define ia64_get_rr(index) \ -({ \ - __u64 ia64_intri_res; \ - \ - __asm__ __volatile__ ("mov %0=rr[%1]" : "=r"(ia64_intri_res) : "r" \ - (index)); \ - \ - ia64_intri_res; \ +#define ia64_get_rr(index) \ +({ \ + __u64 ia64_intri_res; \ + asm volatile ("mov %0=rr[%1]" : "=r"(ia64_intri_res) : "r" (index)); \ + ia64_intri_res; \ }) - -#define ia64_fc(addr) \ - __asm__ __volatile__ ("fc %0" :: "r"(addr) : "memory"); - - -#define ia64_sync_i() \ - __asm__ __volatile__ (";; sync.i" ::: "memory") - -#define ia64_ssm(mask) __asm__ __volatile__ ("ssm %0":: "i"((mask)) : "memory"); -#define ia64_rsm(mask) __asm__ __volatile__ ("rsm %0":: "i"((mask)) : "memory"); -#define ia64_sum(mask) __asm__ __volatile__ ("sum %0":: "i"((mask)) : "memory"); -#define ia64_rum(mask) __asm__ __volatile__ ("rum %0":: "i"((mask)) : "memory"); - -#define ia64_ptce(addr) \ - __asm__ __volatile__ ("ptc.e %0" :: "r"(addr)) +#define ia64_fc(addr) asm volatile ("fc %0" :: "r"(addr) : "memory") -#define ia64_ptcga(addr, size) \ - __asm__ __volatile__ ("ptc.ga %0,%1" :: "r"(addr), "r"(size) : "memory") +#define ia64_sync_i() asm volatile (";; sync.i" ::: "memory") +#define ia64_ssm(mask) asm volatile ("ssm %0":: "i"((mask)) : "memory") +#define ia64_rsm(mask) asm volatile ("rsm %0":: "i"((mask)) : "memory") +#define ia64_sum(mask) asm volatile ("sum %0":: "i"((mask)) : "memory") +#define ia64_rum(mask) asm volatile ("rum %0":: "i"((mask)) : "memory") -#define ia64_ptcl(addr, size) \ - __asm__ __volatile__ ("ptc.l %0,%1" :: "r"(addr), "r"(size) : "memory") +#define ia64_ptce(addr) asm volatile ("ptc.e %0" :: "r"(addr)) +#define ia64_ptcga(addr, size) \ + asm volatile ("ptc.ga %0,%1" :: "r"(addr), "r"(size) : "memory") -#define ia64_ptri(addr, size) \ - __asm__ __volatile__ ("ptr.i %0,%1" :: "r"(addr), "r"(size) : "memory") +#define ia64_ptcl(addr, size) \ + asm volatile ("ptc.l %0,%1" :: "r"(addr), "r"(size) : "memory") +#define ia64_ptri(addr, size) \ + asm volatile ("ptr.i %0,%1" :: "r"(addr), "r"(size) : "memory") -#define ia64_ptrd(addr, size) \ - __asm__ __volatile__ ("ptr.d %0,%1" :: "r"(addr), "r"(size) : "memory") +#define ia64_ptrd(addr, size) \ + asm volatile ("ptr.d %0,%1" :: "r"(addr), "r"(size) : "memory") /* Values for lfhint in ia64_lfetch and ia64_lfetch_fault */ @@ -548,38 +500,38 @@ extern void ia64_bad_param_for_getreg(void); #define ia64_lfhint_nt2 2 #define ia64_lfhint_nta 3 -#define ia64_lfetch(lfhint, y) \ -({ \ - switch (lfhint) { \ - case ia64_lfhint_none: \ - __asm__ __volatile__ ("lfetch [%0]" : : "r"(y)); \ - break; \ - case ia64_lfhint_nt1: \ - __asm__ __volatile__ ("lfetch.nt1 [%0]" : : "r"(y)); \ - break; \ - case ia64_lfhint_nt2: \ - __asm__ __volatile__ ("lfetch.nt2 [%0]" : : "r"(y)); \ - break; \ - case ia64_lfhint_nta: \ - __asm__ __volatile__ ("lfetch.nta [%0]" : : "r"(y)); \ - break; \ - } \ +#define ia64_lfetch(lfhint, y) \ +({ \ + switch (lfhint) { \ + case ia64_lfhint_none: \ + asm volatile ("lfetch [%0]" : : "r"(y)); \ + break; \ + case ia64_lfhint_nt1: \ + asm volatile ("lfetch.nt1 [%0]" : : "r"(y)); \ + break; \ + case ia64_lfhint_nt2: \ + asm volatile ("lfetch.nt2 [%0]" : : "r"(y)); \ + break; \ + case ia64_lfhint_nta: \ + asm volatile ("lfetch.nta [%0]" : : "r"(y)); \ + break; \ + } \ }) #define ia64_lfetch_excl(lfhint, y) \ ({ \ switch (lfhint) { \ case ia64_lfhint_none: \ - __asm__ __volatile__ ("lfetch.excl [%0]" :: "r"(y)); \ + asm volatile ("lfetch.excl [%0]" :: "r"(y)); \ break; \ case ia64_lfhint_nt1: \ - __asm__ __volatile__ ("lfetch.excl.nt1 [%0]" :: "r"(y));\ + asm volatile ("lfetch.excl.nt1 [%0]" :: "r"(y)); \ break; \ case ia64_lfhint_nt2: \ - __asm__ __volatile__ ("lfetch.excl.nt2 [%0]" :: "r"(y));\ + asm volatile ("lfetch.excl.nt2 [%0]" :: "r"(y)); \ break; \ case ia64_lfhint_nta: \ - __asm__ __volatile__ ("lfetch.excl.nta [%0]" :: "r"(y));\ + asm volatile ("lfetch.excl.nta [%0]" :: "r"(y)); \ break; \ } \ }) @@ -588,16 +540,16 @@ extern void ia64_bad_param_for_getreg(void); ({ \ switch (lfhint) { \ case ia64_lfhint_none: \ - __asm__ __volatile__ ("lfetch.fault [%0]" : : "r"(y)); \ + asm volatile ("lfetch.fault [%0]" : : "r"(y)); \ break; \ case ia64_lfhint_nt1: \ - __asm__ __volatile__ ("lfetch.fault.nt1 [%0]" : : "r"(y)); \ + asm volatile ("lfetch.fault.nt1 [%0]" : : "r"(y)); \ break; \ case ia64_lfhint_nt2: \ - __asm__ __volatile__ ("lfetch.fault.nt2 [%0]" : : "r"(y)); \ + asm volatile ("lfetch.fault.nt2 [%0]" : : "r"(y)); \ break; \ case ia64_lfhint_nta: \ - __asm__ __volatile__ ("lfetch.fault.nta [%0]" : : "r"(y)); \ + asm volatile ("lfetch.fault.nta [%0]" : : "r"(y)); \ break; \ } \ }) @@ -606,28 +558,27 @@ extern void ia64_bad_param_for_getreg(void); ({ \ switch (lfhint) { \ case ia64_lfhint_none: \ - __asm__ __volatile__ ("lfetch.fault.excl [%0]" :: "r"(y)); \ + asm volatile ("lfetch.fault.excl [%0]" :: "r"(y)); \ break; \ case ia64_lfhint_nt1: \ - __asm__ __volatile__ ("lfetch.fault.excl.nt1 [%0]" :: "r"(y)); \ + asm volatile ("lfetch.fault.excl.nt1 [%0]" :: "r"(y)); \ break; \ case ia64_lfhint_nt2: \ - __asm__ __volatile__ ("lfetch.fault.excl.nt2 [%0]" :: "r"(y)); \ + asm volatile ("lfetch.fault.excl.nt2 [%0]" :: "r"(y)); \ break; \ case ia64_lfhint_nta: \ - __asm__ __volatile__ ("lfetch.fault.excl.nta [%0]" :: "r"(y)); \ + asm volatile ("lfetch.fault.excl.nta [%0]" :: "r"(y)); \ break; \ } \ }) -#define ia64_intrin_local_irq_restore(x) \ -do { \ - __asm__ __volatile__ ("cmp.ne p6,p7=%0,r0;;" \ - "(p6) ssm psr.i;" \ - "(p7) rsm psr.i;;" \ - "(p6) srlz.d" \ - : : "r"((x)) \ - : "p6", "p7", "memory"); \ +#define ia64_intrin_local_irq_restore(x) \ +do { \ + asm volatile (" cmp.ne p6,p7=%0,r0;;" \ + "(p6) ssm psr.i;" \ + "(p7) rsm psr.i;;" \ + "(p6) srlz.d" \ + :: "r"((x)) : "p6", "p7", "memory"); \ } while (0) #endif /* _ASM_IA64_GCC_INTRIN_H */ diff --git a/include/asm-ia64/ia64regs.h b/include/asm-ia64/ia64regs.h index 3ddfa3128667f..1757f1c11ad4b 100644 --- a/include/asm-ia64/ia64regs.h +++ b/include/asm-ia64/ia64regs.h @@ -8,8 +8,11 @@ #define _ASM_IA64_IA64REGS_H /* -** Register Names for getreg() and setreg() -*/ + * Register Names for getreg() and setreg(). + * + * The "magic" numbers happen to match the values used by the Intel compiler's + * getreg()/setreg() intrinsics. + */ /* Special Registers */ @@ -17,15 +20,15 @@ #define _IA64_REG_PSR 1019 #define _IA64_REG_PSR_L 1019 - // General Integer Registers +/* General Integer Registers */ -#define _IA64_REG_GP 1025 /* R1 */ -#define _IA64_REG_R8 1032 /* R8 */ -#define _IA64_REG_R9 1033 /* R9 */ -#define _IA64_REG_SP 1036 /* R12 */ -#define _IA64_REG_TP 1037 /* R13 */ +#define _IA64_REG_GP 1025 /* R1 */ +#define _IA64_REG_R8 1032 /* R8 */ +#define _IA64_REG_R9 1033 /* R9 */ +#define _IA64_REG_SP 1036 /* R12 */ +#define _IA64_REG_TP 1037 /* R13 */ - /* Application Registers */ +/* Application Registers */ #define _IA64_REG_AR_KR0 3072 #define _IA64_REG_AR_KR1 3073 @@ -55,7 +58,7 @@ #define _IA64_REG_AR_LC 3137 #define _IA64_REG_AR_EC 3138 - /* Control Registers */ +/* Control Registers */ #define _IA64_REG_CR_DCR 4096 #define _IA64_REG_CR_ITM 4097 @@ -84,7 +87,7 @@ #define _IA64_REG_CR_LRR0 4176 #define _IA64_REG_CR_LRR1 4177 - /* Indirect Registers for getindreg() and setindreg() */ +/* Indirect Registers for getindreg() and setindreg() */ #define _IA64_REG_INDR_CPUID 9000 /* getindreg only */ #define _IA64_REG_INDR_DBR 9001 @@ -94,5 +97,4 @@ #define _IA64_REG_INDR_PMD 9005 #define _IA64_REG_INDR_RR 9006 - #endif /* _ASM_IA64_IA64REGS_H */ diff --git a/include/asm-ia64/intrinsics.h b/include/asm-ia64/intrinsics.h index 16d21d49a1bc8..743049ca08516 100644 --- a/include/asm-ia64/intrinsics.h +++ b/include/asm-ia64/intrinsics.h @@ -14,9 +14,9 @@ /* include compiler specific intrinsics */ #include #ifdef __INTEL_COMPILER -#include +# include #else -#include +# include #endif /* @@ -117,7 +117,7 @@ extern void ia64_xchg_called_with_bad_pointer (void); * This function doesn't exist, so you'll get a linker error * if something tries to do an invalid cmpxchg(). */ -extern long ia64_cmpxchg_called_with_bad_pointer(void); +extern long ia64_cmpxchg_called_with_bad_pointer (void); #define ia64_cmpxchg(sem,ptr,old,new,size) \ ({ \ diff --git a/include/asm-ia64/io.h b/include/asm-ia64/io.h index e02f403a23398..297efb06c3478 100644 --- a/include/asm-ia64/io.h +++ b/include/asm-ia64/io.h @@ -52,10 +52,10 @@ extern unsigned int num_io_spaces; # ifdef __KERNEL__ +#include #include #include #include -#include /* * Change virtual addresses to physical addresses and vv. diff --git a/include/asm-ia64/page.h b/include/asm-ia64/page.h index 8372da8cad5d6..56f5c49a4e958 100644 --- a/include/asm-ia64/page.h +++ b/include/asm-ia64/page.h @@ -9,8 +9,8 @@ #include -#include #include +#include /* * PAGE_SHIFT determines the actual kernel page size. diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h index c225163a49b25..c6b4af2b3643a 100644 --- a/include/asm-ia64/processor.h +++ b/include/asm-ia64/processor.h @@ -15,10 +15,10 @@ #include -#include +#include #include +#include #include -#include #define IA64_NUM_DBG_REGS 8 /* @@ -357,13 +357,12 @@ extern unsigned long get_wchan (struct task_struct *p); /* Return stack pointer of blocked task TSK. */ #define KSTK_ESP(tsk) ((tsk)->thread.ksp) -extern void ia64_getreg_unknown_kr(void); -extern void ia64_setreg_unknown_kr(void); - +extern void ia64_getreg_unknown_kr (void); +extern void ia64_setreg_unknown_kr (void); #define ia64_get_kr(regnum) \ ({ \ - unsigned long r=0; \ + unsigned long r = 0; \ \ switch (regnum) { \ case 0: r = ia64_getreg(_IA64_REG_AR_KR0); break; \ @@ -646,18 +645,18 @@ ia64_get_dbr (__u64 regnum) /* XXX remove the handcoded version once we have a sufficiently clever compiler... */ #ifdef SMART_COMPILER -# define ia64_rotr(w,n) \ - ({ \ - __u64 _w = (w), _n = (n); \ - \ - (_w >> _n) | (_w << (64 - _n)); \ +# define ia64_rotr(w,n) \ + ({ \ + __u64 __ia64_rotr_w = (w), _n = (n); \ + \ + (__ia64_rotr_w >> _n) | (__ia64_rotr_w << (64 - _n)); \ }) #else -# define ia64_rotr(w,n) \ - ({ \ - __u64 result; \ - result = ia64_shrp((w), (w), (n)); \ - result; \ +# define ia64_rotr(w,n) \ + ({ \ + __u64 __ia64_rotr_w; \ + __ia64_rotr_w = ia64_shrp((w), (w), (n)); \ + __ia64_rotr_w; \ }) #endif diff --git a/include/asm-ia64/rwsem.h b/include/asm-ia64/rwsem.h index 4921b76fdfb9f..6ece5061dc190 100644 --- a/include/asm-ia64/rwsem.h +++ b/include/asm-ia64/rwsem.h @@ -22,6 +22,7 @@ #include #include + #include /* @@ -82,9 +83,7 @@ init_rwsem (struct rw_semaphore *sem) static inline void __down_read (struct rw_semaphore *sem) { - int result; - - result = ia64_fetchadd4_acq((unsigned int *)&sem->count, 1); + int result = ia64_fetchadd4_acq((unsigned int *)&sem->count, 1); if (result < 0) rwsem_down_read_failed(sem); @@ -113,9 +112,7 @@ __down_write (struct rw_semaphore *sem) static inline void __up_read (struct rw_semaphore *sem) { - int result; - - result = ia64_fetchadd4_rel((unsigned int *)&sem->count, -1); + int result = ia64_fetchadd4_rel((unsigned int *)&sem->count, -1); if (result < 0 && (--result & RWSEM_ACTIVE_MASK) == 0) rwsem_wake(sem); diff --git a/include/asm-ia64/siginfo.h b/include/asm-ia64/siginfo.h index 16de6f10c1e1f..eca7d714a8fb0 100644 --- a/include/asm-ia64/siginfo.h +++ b/include/asm-ia64/siginfo.h @@ -79,7 +79,6 @@ typedef struct siginfo { * si_code is non-zero and __ISR_VALID is set in si_flags. */ #define si_isr _sifields._sigfault._isr -#define si_pfm_ovfl _sifields._sigprof._pfm_ovfl_counters /* * Flag values for si_flags: diff --git a/include/asm-ia64/smp.h b/include/asm-ia64/smp.h index 5da8160993499..09e923da68932 100644 --- a/include/asm-ia64/smp.h +++ b/include/asm-ia64/smp.h @@ -120,7 +120,7 @@ hard_smp_processor_id (void) unsigned long bits; } lid; - lid.bits = ia64_getreg(_IA64_REG_CR_LID); + lid.bits = ia64_getreg(_IA64_REG_CR_LID); return lid.f.id << 8 | lid.f.eid; } diff --git a/include/asm-ia64/spinlock.h b/include/asm-ia64/spinlock.h index ca3a254779494..3a5f08f4c6f23 100644 --- a/include/asm-ia64/spinlock.h +++ b/include/asm-ia64/spinlock.h @@ -9,13 +9,13 @@ * This file is used for SMP configurations only. */ -#include #include +#include -#include -#include #include +#include #include +#include typedef struct { volatile unsigned int lock; diff --git a/include/asm-ia64/system.h b/include/asm-ia64/system.h index 5c59cb6b8d19a..c0a6384028584 100644 --- a/include/asm-ia64/system.h +++ b/include/asm-ia64/system.h @@ -113,19 +113,17 @@ extern struct ia64_boot_param { /* clearing psr.i is implicitly serialized (visible by next insn) */ /* setting psr.i requires data serialization */ -#define __local_irq_save(x) \ -do { \ - unsigned long psr; \ - psr = ia64_getreg(_IA64_REG_PSR); \ - ia64_stop(); \ - ia64_rsm(IA64_PSR_I); \ - (x) = psr; \ +#define __local_irq_save(x) \ +do { \ + (x) = ia64_getreg(_IA64_REG_PSR); \ + ia64_stop(); \ + ia64_rsm(IA64_PSR_I); \ } while (0) -#define __local_irq_disable() \ -do { \ - ia64_stop(); \ - ia64_rsm(IA64_PSR_I); \ +#define __local_irq_disable() \ +do { \ + ia64_stop(); \ + ia64_rsm(IA64_PSR_I); \ } while (0) #define __local_irq_restore(x) ia64_intrin_local_irq_restore((x) & IA64_PSR_I) @@ -165,13 +163,13 @@ do { \ #endif /* !CONFIG_IA64_DEBUG_IRQ */ #define local_irq_enable() ({ ia64_ssm(IA64_PSR_I); ia64_srlz_d(); }) -#define local_save_flags(flags) ({ (flags) = ia64_getreg(_IA64_REG_PSR); }) +#define local_save_flags(flags) ((flags) = ia64_getreg(_IA64_REG_PSR)) #define irqs_disabled() \ ({ \ - unsigned long flags; \ - local_save_flags(flags); \ - (flags & IA64_PSR_I) == 0; \ + unsigned long __ia64_id_flags; \ + local_save_flags(__ia64_id_flags); \ + (__ia64_id_flags & IA64_PSR_I) == 0; \ }) #ifdef __KERNEL__ diff --git a/include/asm-ia64/timex.h b/include/asm-ia64/timex.h index df9085722e6b5..414aae0604409 100644 --- a/include/asm-ia64/timex.h +++ b/include/asm-ia64/timex.h @@ -10,8 +10,8 @@ * Also removed cacheflush_time as it's entirely unused. */ -#include #include +#include typedef unsigned long cycles_t; diff --git a/include/asm-ia64/tlbflush.h b/include/asm-ia64/tlbflush.h index 62d0d466f5476..049c69845b23c 100644 --- a/include/asm-ia64/tlbflush.h +++ b/include/asm-ia64/tlbflush.h @@ -10,9 +10,9 @@ #include +#include #include #include -#include /* * Now for some TLB flushing routines. This is the kind of stuff that diff --git a/include/asm-ia64/unistd.h b/include/asm-ia64/unistd.h index f28ad25550a45..f65623c70fb1c 100644 --- a/include/asm-ia64/unistd.h +++ b/include/asm-ia64/unistd.h @@ -342,8 +342,10 @@ extern pid_t clone (unsigned long flags, void *sp); /* * "Conditional" syscalls * - * Note, this macro can only be used in the - * file which defines sys_ni_syscall, i.e., in kernel/sys.c. + * Note, this macro can only be used in the file which defines sys_ni_syscall, i.e., in + * kernel/sys.c. This version causes warnings because the declaration isn't a + * proper prototype, but we can't use __typeof__ either, because not all cond_syscall() + * declarations have prototypes at the moment. */ #define cond_syscall(x) asmlinkage long x() __attribute__((weak,alias("sys_ni_syscall"))); -- 2.53.0