From 60c22e3fce215069fa8dbe385b5cfb72cadf138c Mon Sep 17 00:00:00 2001 From: Darren Williams Date: Tue, 1 Jun 2004 08:40:42 -0700 Subject: [PATCH] ia64: define pending_irq_cpumask in irq.c This fixes a build-problem with the Ski simulator. The simulator doesn't include iosapic.c and hence pending_irq_cpumask never got defined. --- arch/ia64/kernel/iosapic.c | 2 +- arch/ia64/kernel/irq.c | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/ia64/kernel/iosapic.c b/arch/ia64/kernel/iosapic.c index 33044bcb1494e..9ef5f3ef9dcba 100644 --- a/arch/ia64/kernel/iosapic.c +++ b/arch/ia64/kernel/iosapic.c @@ -100,7 +100,7 @@ #endif static spinlock_t iosapic_lock = SPIN_LOCK_UNLOCKED; -cpumask_t __cacheline_aligned pending_irq_cpumask[NR_IRQS]; +extern cpumask_t __cacheline_aligned pending_irq_cpumask[NR_IRQS]; /* These tables map IA-64 vectors to the IOSAPIC pin that generates this vector. */ diff --git a/arch/ia64/kernel/irq.c b/arch/ia64/kernel/irq.c index 37c17881d882d..42056fbaa151e 100644 --- a/arch/ia64/kernel/irq.c +++ b/arch/ia64/kernel/irq.c @@ -56,7 +56,6 @@ #include #include -extern cpumask_t __cacheline_aligned pending_irq_cpumask[NR_IRQS]; /* * Linux has a controller-independent x86 interrupt architecture. @@ -85,6 +84,11 @@ irq_desc_t _irq_desc[NR_IRQS] __cacheline_aligned = { } }; +/* + * This is updated when the user sets irq affinity via /proc + */ +cpumask_t __cacheline_aligned pending_irq_cpumask[NR_IRQS]; + #ifdef CONFIG_IA64_GENERIC irq_desc_t * __ia64_irq_desc (unsigned int irq) { -- 2.53.0