From 9b4c1048a6f13d3f350d67d549c83b70b4607211 Mon Sep 17 00:00:00 2001 From: Dave Jones Date: Wed, 26 Feb 2003 16:44:30 -0800 Subject: [PATCH] [PATCH] Enable SSE on newer Athlons. --- arch/i386/kernel/cpu/amd.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/i386/kernel/cpu/amd.c b/arch/i386/kernel/cpu/amd.c index 762a1a8d8c013..fc57a582354e8 100644 --- a/arch/i386/kernel/cpu/amd.c +++ b/arch/i386/kernel/cpu/amd.c @@ -151,11 +151,10 @@ static void __init init_amd(struct cpuinfo_x86 *c) case 6: /* An Athlon/Duron */ /* Bit 15 of Athlon specific MSR 15, needs to be 0 - * to enable SSE on Palomino/Morgan CPU's. - * If the BIOS didn't enable it already, enable it - * here. + * to enable SSE on Palomino/Morgan/Barton CPU's. + * If the BIOS didn't enable it already, enable it here. */ - if (c->x86_model == 6 || c->x86_model == 7) { + if (c->x86_model >= 6 && c->x86_model <= 10) { if (!cpu_has(c, X86_FEATURE_XMM)) { printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); rdmsr(MSR_K7_HWCR, l, h); -- 2.53.0