From a8786db8474f0bca1e28ae1692e92c86a31689ab Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Sun, 20 Jul 2003 18:37:25 -0700 Subject: [PATCH] [SPARC64]: Read processor number correctly on Ultra-IIIi/Jalapeno. --- arch/sparc64/kernel/entry.S | 9 +++++++-- arch/sparc64/kernel/head.S | 7 +++++++ arch/sparc64/kernel/irq.c | 24 ++++++++++++++++++------ include/asm-sparc64/asi.h | 1 + include/asm-sparc64/head.h | 11 +++++++++++ include/asm-sparc64/irq.h | 1 + include/asm-sparc64/smp.h | 18 +++++++++++++----- 7 files changed, 58 insertions(+), 13 deletions(-) diff --git a/arch/sparc64/kernel/entry.S b/arch/sparc64/kernel/entry.S index df3ff3d09a6b5..975279fdad94f 100644 --- a/arch/sparc64/kernel/entry.S +++ b/arch/sparc64/kernel/entry.S @@ -911,10 +911,15 @@ cee_trap: sllx %g1, 63, %g2; \ or %g4, %g2, %g4; \ /* Get log entry pointer for this cpu at this trap level. */ \ + BRANCH_IF_JALAPENO(g2,g3,50f) \ ldxa [%g0] ASI_SAFARI_CONFIG, %g2; \ srlx %g2, 17, %g2; \ - and %g2, 0x3ff, %g2; \ - sllx %g2, 9, %g2; \ + ba,pt %xcc, 60f; \ + and %g2, 0x3ff, %g2; \ +50: ldxa [%g0] ASI_JBUS_CONFIG, %g2; \ + srlx %g2, 17, %g2; \ + and %g2, 0x1f, %g2; \ +60: sllx %g2, 9, %g2; \ sethi %hi(cheetah_error_log), %g3; \ ldx [%g3 + %lo(cheetah_error_log)], %g3; \ brz,pn %g3, 80f; \ diff --git a/arch/sparc64/kernel/head.S b/arch/sparc64/kernel/head.S index 2f3ae537250df..dfc500908ef95 100644 --- a/arch/sparc64/kernel/head.S +++ b/arch/sparc64/kernel/head.S @@ -645,11 +645,18 @@ spitfire_vpte_base: nop not_starfire: + BRANCH_IF_JALAPENO(g1,g5,is_jalapeno) BRANCH_IF_ANY_CHEETAH(g1,g5,is_cheetah) ba,pt %xcc, not_cheetah nop +is_jalapeno: + ldxa [%g0] ASI_JBUS_CONFIG, %g1 + srlx %g1, 17, %g1 + ba,pt %xcc, set_worklist + and %g1, 0x1f, %g1 ! 5bit JBUS ID + is_cheetah: ldxa [%g0] ASI_SAFARI_CONFIG, %g1 srlx %g1, 17, %g1 diff --git a/arch/sparc64/kernel/irq.c b/arch/sparc64/kernel/irq.c index c606b4721b590..dd39c59a82d26 100644 --- a/arch/sparc64/kernel/irq.c +++ b/arch/sparc64/kernel/irq.c @@ -162,12 +162,24 @@ void enable_irq(unsigned int irq) return; if (tlb_type == cheetah || tlb_type == cheetah_plus) { - /* We set it to our Safari AID. */ - __asm__ __volatile__("ldxa [%%g0] %1, %0" - : "=r" (tid) - : "i" (ASI_SAFARI_CONFIG)); - tid = ((tid & (0x3ffUL<<17)) << 9); - tid &= IMAP_AID_SAFARI; + unsigned long ver; + + __asm__ ("rdpr %%ver, %0" : "=r" (ver)); + if ((ver >> 32) == 0x003e0016) { + /* We set it to our JBUS ID. */ + __asm__ __volatile__("ldxa [%%g0] %1, %0" + : "=r" (tid) + : "i" (ASI_JBUS_CONFIG)); + tid = ((tid & (0x1fUL<<17)) << 9); + tid &= IMAP_TID_JBUS; + } else { + /* We set it to our Safari AID. */ + __asm__ __volatile__("ldxa [%%g0] %1, %0" + : "=r" (tid) + : "i" (ASI_SAFARI_CONFIG)); + tid = ((tid & (0x3ffUL<<17)) << 9); + tid &= IMAP_AID_SAFARI; + } } else if (this_is_starfire == 0) { /* We set it to our UPA MID. */ __asm__ __volatile__("ldxa [%%g0] %1, %0" diff --git a/include/asm-sparc64/asi.h b/include/asm-sparc64/asi.h index d0796a10c2221..81143273017f1 100644 --- a/include/asm-sparc64/asi.h +++ b/include/asm-sparc64/asi.h @@ -51,6 +51,7 @@ #define ASI_INTR_DISPATCH_STAT 0x48 /* IRQ vector dispatch status */ #define ASI_INTR_RECEIVE 0x49 /* IRQ vector receive status */ #define ASI_UPA_CONFIG 0x4a /* UPA config space */ +#define ASI_JBUS_CONFIG 0x4a /* (IIIi) JBUS Config Register */ #define ASI_SAFARI_CONFIG 0x4a /* (III) Safari Config Register */ #define ASI_SAFARI_ADDRESS 0x4a /* (III) Safari Address Register */ #define ASI_ESTATE_ERROR_EN 0x4b /* E-cache error enable space */ diff --git a/include/asm-sparc64/head.h b/include/asm-sparc64/head.h index c3ab5543edf4c..b63a33cf49718 100644 --- a/include/asm-sparc64/head.h +++ b/include/asm-sparc64/head.h @@ -9,10 +9,12 @@ #define PTREGS_OFF (STACK_BIAS + STACKFRAME_SZ) #define __CHEETAH_ID 0x003e0014 +#define __JALAPENO_ID 0x003e0016 #define CHEETAH_MANUF 0x003e #define CHEETAH_IMPL 0x0014 #define CHEETAH_PLUS_IMPL 0x0015 +#define JALAPENO_IMPL 0x0016 #define BRANCH_IF_CHEETAH_BASE(tmp1,tmp2,label) \ rdpr %ver, %tmp1; \ @@ -23,6 +25,15 @@ be,pn %icc, label; \ nop; +#define BRANCH_IF_JALAPENO(tmp1,tmp2,label) \ + rdpr %ver, %tmp1; \ + sethi %hi(__JALAPENO_ID), %tmp2; \ + srlx %tmp1, 32, %tmp1; \ + or %tmp2, %lo(__JALAPENO_ID), %tmp2;\ + cmp %tmp1, %tmp2; \ + be,pn %icc, label; \ + nop; + #define BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(tmp1,tmp2,label) \ rdpr %ver, %tmp1; \ srlx %tmp1, (32 + 16), %tmp2; \ diff --git a/include/asm-sparc64/irq.h b/include/asm-sparc64/irq.h index 450b9a5fb9944..aa3de3bc9d222 100644 --- a/include/asm-sparc64/irq.h +++ b/include/asm-sparc64/irq.h @@ -78,6 +78,7 @@ extern unsigned char dma_sync_reg_table_entry; /* IMAP/ICLR register defines */ #define IMAP_VALID 0x80000000 /* IRQ Enabled */ #define IMAP_TID_UPA 0x7c000000 /* UPA TargetID */ +#define IMAP_TID_JBUS 0x7c000000 /* JBUS TargetID */ #define IMAP_AID_SAFARI 0x7c000000 /* Safari AgentID */ #define IMAP_NID_SAFARI 0x03e00000 /* Safari NodeID */ #define IMAP_IGN 0x000007c0 /* IRQ Group Number */ diff --git a/include/asm-sparc64/smp.h b/include/asm-sparc64/smp.h index fab5999a9a75d..533bbe729a1b7 100644 --- a/include/asm-sparc64/smp.h +++ b/include/asm-sparc64/smp.h @@ -94,11 +94,19 @@ static inline unsigned int any_online_cpu(unsigned long mask) static __inline__ int hard_smp_processor_id(void) { if (tlb_type == cheetah || tlb_type == cheetah_plus) { - unsigned long safari_config; - __asm__ __volatile__("ldxa [%%g0] %1, %0" - : "=r" (safari_config) - : "i" (ASI_SAFARI_CONFIG)); - return ((safari_config >> 17) & 0x3ff); + unsigned long cfg, ver; + __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver)); + if ((ver >> 32) == 0x003e0016) { + __asm__ __volatile__("ldxa [%%g0] %1, %0" + : "=r" (cfg) + : "i" (ASI_JBUS_CONFIG)); + return ((cfg >> 17) & 0x1f); + } else { + __asm__ __volatile__("ldxa [%%g0] %1, %0" + : "=r" (cfg) + : "i" (ASI_SAFARI_CONFIG)); + return ((cfg >> 17) & 0x3ff); + } } else if (this_is_starfire != 0) { return starfire_hard_smp_processor_id(); } else { -- 2.53.0