From af0c8a6ce4b86c4c3475a96ed2e542566f082577 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Tue, 7 Sep 2004 19:11:45 +0100 Subject: [PATCH] [ARM PATCH] 2052/2: extra IRQ handling for PXA27x Patch from Nicolas Pitre Signed-off-by: Nicolas Pitre --- arch/arm/mach-pxa/irq.c | 94 +++++++++++++++++++++++++-------- include/asm-arm/arch-pxa/irqs.h | 54 ++++++++++++++----- 2 files changed, 114 insertions(+), 34 deletions(-) diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index c771e43761e28..df5d469a59b06 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -25,34 +25,58 @@ /* - * This is for IRQs known as PXA_IRQ([8...31]). + * This is for peripheral IRQs internal to the PXA chip. */ -static void pxa_mask_irq(unsigned int irq) +static void pxa_mask_low_irq(unsigned int irq) { ICMR &= ~(1 << (irq + PXA_IRQ_SKIP)); } -static void pxa_unmask_irq(unsigned int irq) +static void pxa_unmask_low_irq(unsigned int irq) { ICMR |= (1 << (irq + PXA_IRQ_SKIP)); } -static struct irqchip pxa_internal_chip = { - .ack = pxa_mask_irq, - .mask = pxa_mask_irq, - .unmask = pxa_unmask_irq, +static struct irqchip pxa_internal_chip_low = { + .ack = pxa_mask_low_irq, + .mask = pxa_mask_low_irq, + .unmask = pxa_unmask_low_irq, }; +#if PXA_INTERNAL_IRQS > 32 + +/* + * This is for the second set of internal IRQs as found on the PXA27x. + */ + +static void pxa_mask_high_irq(unsigned int irq) +{ + ICMR2 &= ~(1 << (irq - 32 + PXA_IRQ_SKIP)); +} + +static void pxa_unmask_high_irq(unsigned int irq) +{ + ICMR2 |= (1 << (irq - 32 + PXA_IRQ_SKIP)); +} + +static struct irqchip pxa_internal_chip_high = { + .ack = pxa_mask_high_irq, + .mask = pxa_mask_high_irq, + .unmask = pxa_unmask_high_irq, +}; + +#endif + /* * PXA GPIO edge detection for IRQs: * IRQs are generated on Falling-Edge, Rising-Edge, or both. * Use this instead of directly setting GRER/GFER. */ -static long GPIO_IRQ_rising_edge[3]; -static long GPIO_IRQ_falling_edge[3]; -static long GPIO_IRQ_mask[3]; +static long GPIO_IRQ_rising_edge[4]; +static long GPIO_IRQ_falling_edge[4]; +static long GPIO_IRQ_mask[4]; static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) { @@ -106,13 +130,13 @@ static void pxa_ack_low_gpio(unsigned int irq) static struct irqchip pxa_low_gpio_chip = { .ack = pxa_ack_low_gpio, - .mask = pxa_mask_irq, - .unmask = pxa_unmask_irq, + .mask = pxa_mask_low_irq, + .unmask = pxa_unmask_low_irq, .type = pxa_gpio_irq_type, }; /* - * Demux handler for GPIO 2-80 edge detect interrupts + * Demux handler for GPIO>=2 edge detect interrupts */ static void pxa_gpio_demux_handler(unsigned int irq, struct irqdesc *desc, @@ -169,6 +193,23 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irqdesc *desc, } while (mask); loop = 1; } + +#if PXA_LAST_GPIO >= 96 + mask = GEDR3; + if (mask) { + GEDR3 = mask; + irq = IRQ_GPIO(96); + desc = irq_desc + irq; + do { + if (mask & 1) + desc->handle(irq, desc, regs); + irq++; + desc++; + mask >>= 1; + } while (mask); + loop = 1; + } +#endif } while (loop); } @@ -208,17 +249,18 @@ void __init pxa_init_irq(void) int irq; /* disable all IRQs */ - ICMR = 0; + ICMR = ICMR2 = 0; /* all IRQs are IRQ, not FIQ */ - ICLR = 0; + ICLR = ICLR2 = 0; /* clear all GPIO edge detects */ - GFER0 = GFER1 = GFER2 = 0; - GRER0 = GRER1 = GRER2 = 0; + GFER0 = GFER1 = GFER2 = GFER3 = 0; + GRER0 = GRER1 = GRER2 = GRER3 = 0; GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; + GEDR3 = GEDR3; /* only unmasked interrupts kick us out of idle */ ICCR = 1; @@ -227,10 +269,18 @@ void __init pxa_init_irq(void) GPIO_IRQ_mask[0] = 3; for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) { - set_irq_chip(irq, &pxa_internal_chip); + set_irq_chip(irq, &pxa_internal_chip_low); + set_irq_handler(irq, do_level_IRQ); + set_irq_flags(irq, IRQF_VALID); + } + +#if PXA_INTERNAL_IRQS > 32 + for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) { + set_irq_chip(irq, &pxa_internal_chip_high); set_irq_handler(irq, do_level_IRQ); set_irq_flags(irq, IRQF_VALID); } +#endif for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { set_irq_chip(irq, &pxa_low_gpio_chip); @@ -238,13 +288,13 @@ void __init pxa_init_irq(void) set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } - for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(80); irq++) { + for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) { set_irq_chip(irq, &pxa_muxed_gpio_chip); set_irq_handler(irq, do_edge_IRQ); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } - /* Install handler for GPIO 2-80 edge detect interrupts */ - set_irq_chip(IRQ_GPIO_2_80, &pxa_internal_chip); - set_irq_chained_handler(IRQ_GPIO_2_80, pxa_gpio_demux_handler); + /* Install handler for GPIO>=2 edge detect interrupts */ + set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low); + set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); } diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h index 29164556bd65f..3d9b92a466ca2 100644 --- a/include/asm-arm/arch-pxa/irqs.h +++ b/include/asm-arm/arch-pxa/irqs.h @@ -12,19 +12,34 @@ #include -#define PXA_IRQ_SKIP 7 /* The first 7 IRQs are not yet used */ +#ifdef CONFIG_PXA27x +#define PXA_IRQ_SKIP 0 +#else +#define PXA_IRQ_SKIP 7 +#endif + #define PXA_IRQ(x) ((x) - PXA_IRQ_SKIP) -#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error */ +#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */ +#define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */ +#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */ +#define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI) */ +#define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */ +#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */ +#define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */ +#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */ +#define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */ #define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */ #define IRQ_GPIO1 PXA_IRQ(9) /* GPIO1 Edge Detect */ -#define IRQ_GPIO_2_80 PXA_IRQ(10) /* GPIO[2-80] Edge Detect */ +#define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */ #define IRQ_USB PXA_IRQ(11) /* USB Service */ #define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */ #define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt */ #define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */ -#define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request */ -#define IRQ_NSSP PXA_IRQ(16) /* Network SSP Service Request */ +#define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */ +#define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */ +#define IRQ_NSSP PXA_IRQ(16) /* Network SSP Service Request (PXA25x) */ +#define IRQ_SSP2 PXA_IRQ(16) /* SSP2 interrupt (PXA27x) */ #define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */ #define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */ #define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */ @@ -41,13 +56,28 @@ #define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */ #define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */ -#define GPIO_2_80_TO_IRQ(x) \ - PXA_IRQ((x) - 2 + 32) -#define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_80_TO_IRQ(x)) +#ifdef CONFIG_PXA27x +#define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */ +#define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */ -#define IRQ_TO_GPIO_2_80(i) \ - ((i) - PXA_IRQ(32) + 2) -#define IRQ_TO_GPIO(i) ((i) - (((i) > IRQ_GPIO1) ? IRQ_GPIO(2) - 2 : IRQ_GPIO(0))) +#define PXA_INTERNAL_IRQS 34 +#else +#define PXA_INTERNAL_IRQS 32 +#endif + +#define GPIO_2_x_TO_IRQ(x) \ + PXA_IRQ((x) - 2 + PXA_INTERNAL_IRQS) +#define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x)) + +#define IRQ_TO_GPIO_2_x(i) \ + ((i) - IRQ_GPIO(2) + 2) +#define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i)) + +#if defined(CONFIG_PXA25x) +#define PXA_LAST_GPIO 80 +#elif defined(CONFIG_PXA27x) +#define PXA_LAST_GPIO 127 +#endif /* * The next 16 interrupts are for board specific purposes. Since @@ -55,7 +85,7 @@ * these. If you need more, increase IRQ_BOARD_END, but keep it * within sensible limits. */ -#define IRQ_BOARD_START (IRQ_GPIO(80) + 1) +#define IRQ_BOARD_START (IRQ_GPIO(PXA_LAST_GPIO) + 1) #define IRQ_BOARD_END (IRQ_BOARD_START + 16) #define IRQ_SA1111_START (IRQ_BOARD_END) -- 2.53.0