From cb141c23967ed93463682306ce02f00ac7b94f7e Mon Sep 17 00:00:00 2001 From: Andrew Morton Date: Sun, 18 Jan 2004 18:52:16 -0800 Subject: [PATCH] [PATCH] sn: Added call to pcireg_intr_status_get From: Pat Gefre Added call to pcireg_intr_status_get --- arch/ia64/sn/io/sn2/pcibr/pcibr_reg.c | 66 +++++++++++++++++---------- arch/ia64/sn/kernel/irq.c | 2 +- 2 files changed, 43 insertions(+), 25 deletions(-) diff --git a/arch/ia64/sn/io/sn2/pcibr/pcibr_reg.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_reg.c index 545290f653273..4eafac458710e 100644 --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_reg.c +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_reg.c @@ -6,7 +6,6 @@ * Copyright (C) 2003 Silicon Graphics, Inc. All rights reserved. */ - #include #include #include @@ -24,51 +23,70 @@ uint64_t pcireg_control_get(void *ptr) { - uint64_t ret = 0; - pic_t *bridge; + uint64_t ret = 0; + pic_t *bridge; + + if (IS_IOADDR(ptr)) + bridge = (pic_t *) ptr; + else + bridge = (pic_t *) ((pcibr_soft_t) (ptr))->bs_base; + + ret = ((pic_t *) bridge)->p_wid_control; + return ret; +} + +/* + * Interrupt Status Register Access -- Read Only 0000_0100 + */ +uint64_t +pcireg_intr_status_get(void *ptr) +{ + short bridge_type; + pic_t *bridge; + uint64_t ret = 0; - if ( IS_IOADDR(ptr) ) - bridge = (pic_t *)ptr; + if (IS_IOADDR(ptr)) + bridge = (pic_t *) ptr; else - bridge = (pic_t *)((pcibr_soft_t)(ptr))->bs_base; + bridge = (pic_t *) ((pcibr_soft_t) (ptr))->bs_base; - ret = ((pic_t *)bridge)->p_wid_control; + ret = ((pic_t *) bridge)->p_int_status; return ret; } void pcireg_intr_enable_bit_clr(void *ptr, uint64_t bits) { - pic_t *bridge; + pic_t *bridge; - if ( IS_IOADDR(ptr) ) - bridge = (pic_t *)ptr; + if (IS_IOADDR(ptr)) + bridge = (pic_t *) ptr; else - bridge = (pic_t *)((pcibr_soft_t)(ptr))->bs_base; + bridge = (pic_t *) ((pcibr_soft_t) (ptr))->bs_base; bridge->p_int_enable &= ~bits; } void pcireg_intr_enable_bit_set(void *ptr, uint64_t bits) { - pic_t *bridge; + pic_t *bridge; - if ( IS_IOADDR(ptr) ) - bridge = (pic_t *)ptr; + if (IS_IOADDR(ptr)) + bridge = (pic_t *) ptr; else - bridge = (pic_t *)((pcibr_soft_t)(ptr))->bs_base; + bridge = (pic_t *) ((pcibr_soft_t) (ptr))->bs_base; bridge->p_int_enable |= bits; } void pcireg_intr_addr_addr_set(void *ptr, int int_n, uint64_t addr) { - pic_t *bridge; + pic_t *bridge; - if ( IS_IOADDR(ptr) ) - bridge = (pic_t *)ptr; + if (IS_IOADDR(ptr)) + bridge = (pic_t *) ptr; else - bridge = (pic_t *)((pcibr_soft_t)(ptr))->bs_base; + bridge = (pic_t *) ((pcibr_soft_t) (ptr))->bs_base; bridge->p_int_addr[int_n] &= ~(0x0000FFFFFFFFFFFF); bridge->p_int_addr[int_n] |= (addr & 0x0000FFFFFFFFFFFF); } @@ -79,11 +97,11 @@ pcireg_intr_addr_addr_set(void *ptr, int int_n, uint64_t addr) void pcireg_force_intr_set(void *ptr, int int_n) { - pic_t *bridge; + pic_t *bridge; - if ( IS_IOADDR(ptr) ) - bridge = (pic_t *)ptr; + if (IS_IOADDR(ptr)) + bridge = (pic_t *) ptr; else - bridge = (pic_t *)((pcibr_soft_t)(ptr))->bs_base; - bridge->p_force_pin[int_n] = 1; + bridge = (pic_t *) ((pcibr_soft_t) (ptr))->bs_base; + bridge->p_force_pin[int_n] = 1; } diff --git a/arch/ia64/sn/kernel/irq.c b/arch/ia64/sn/kernel/irq.c index 5cdc94b6d5ac7..85ae658a60a34 100644 --- a/arch/ia64/sn/kernel/irq.c +++ b/arch/ia64/sn/kernel/irq.c @@ -262,7 +262,7 @@ sn_check_intr(int irq, pcibr_intr_t intr) { unsigned long irr_reg; - regval = intr->bi_soft->bs_base->p_int_status_64; + regval = pcireg_intr_status_get(intr->bi_soft->bs_base); irr_reg_num = irq_to_vector(irq) / 64; irr_bit = irq_to_vector(irq) % 64; switch (irr_reg_num) { -- 2.53.0