From dad3cfbd71bf1bff07cb820633ecce9b3072436c Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 19 Oct 2004 16:37:05 +0100 Subject: [PATCH] [SERIAL] Convert TI16C750 flow control into a port capability. Add UART_CAP_AFE, and use this to enable TI16C750 flow control, but only if we have 32 bytes or more of FIFO. --- drivers/serial/8250.c | 13 ++++++++----- drivers/serial/8250.h | 1 + 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c index 6e2e62dec267e..7e63a7fe645ff 100644 --- a/drivers/serial/8250.c +++ b/drivers/serial/8250.c @@ -210,7 +210,7 @@ static const struct serial8250_config uart_config[] = { .tx_loadsz = 64, .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | UART_FCR7_64BYTE, - .flags = UART_CAP_FIFO | UART_CAP_SLEEP, + .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE, }, [PORT_STARTECH] = { .name = "Startech", @@ -1584,11 +1584,14 @@ serial8250_set_termios(struct uart_port *port, struct termios *termios, } /* - * TI16C750: hardware flow control and 64 byte FIFOs. When AFE is - * enabled, RTS will be deasserted when the receive FIFO contains - * more characters than the trigger, or the MCR RTS bit is cleared. + * MCR-based auto flow control. When AFE is enabled, RTS will be + * deasserted when the receive FIFO contains more characters than + * the trigger, or the MCR RTS bit is cleared. In the case where + * the remote UART is not using CTS auto flow control, we must + * have sufficient FIFO entries for the latency of the remote + * UART to respond. IOW, at least 32 bytes of FIFO. */ - if (up->port.type == PORT_16750) { + if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) { up->mcr &= ~UART_MCR_AFE; if (termios->c_cflag & CRTSCTS) up->mcr |= UART_MCR_AFE; diff --git a/drivers/serial/8250.h b/drivers/serial/8250.h index bbf767dbde067..dcf585929ae80 100644 --- a/drivers/serial/8250.h +++ b/drivers/serial/8250.h @@ -47,6 +47,7 @@ struct serial8250_config { #define UART_CAP_FIFO (1 << 8) /* UART has FIFO */ #define UART_CAP_EFR (1 << 9) /* UART has EFR */ #define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */ +#define UART_CAP_AFE (1 << 11) /* MCR-based hw flow control */ #undef SERIAL_DEBUG_PCI -- 2.53.0