From e05d28a519c1d2d1e45702a21b046eb2544261ca Mon Sep 17 00:00:00 2001 From: Dean Roe Date: Wed, 18 Aug 2004 18:01:20 +0000 Subject: [PATCH] [IA64-SGI] report coherence id in /proc/sgi_sn/coherence_id Current SGI Altix systems have a NUMAlink domain size of 1024 compute nodes and are fully cache coherent up to 256 compute nodes (compute nodes are even-numbered). Systems larger than 256 nodes are partitioned into multiple cache coherent systems. This patch exports a partition's coherence id to users via the /proc/sgi_sn/coherence_id file. Signed-off-by: Dean Roe Signed-off-by: Tony Luck --- arch/ia64/sn/kernel/sn2/sn_proc_fs.c | 24 +++++++++++++++++++++++- include/asm-ia64/sn/sn_cpuid.h | 8 +++++++- 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/arch/ia64/sn/kernel/sn2/sn_proc_fs.c b/arch/ia64/sn/kernel/sn2/sn_proc_fs.c index 14840791ac095..3d8f77edac1b4 100644 --- a/arch/ia64/sn/kernel/sn2/sn_proc_fs.c +++ b/arch/ia64/sn/kernel/sn2/sn_proc_fs.c @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000-2003 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved. */ #include #include @@ -118,11 +118,33 @@ register_sn_force_interrupt(void) { } } +static int coherence_id_read_proc(char *page, char **start, off_t off, + int count, int *eof, void *data) { + return sprintf(page, "%d\n", cpuid_to_coherence_id(smp_processor_id())); +} + +void +register_sn_coherence_id(void) { + struct proc_dir_entry *entry; + + if (!sgi_proc_dir) { + sgi_proc_dir = proc_mkdir("sgi_sn", 0); + } + entry = create_proc_entry("coherence_id", 0444, sgi_proc_dir); + if (entry) { + entry->nlink = 1; + entry->data = 0; + entry->read_proc = coherence_id_read_proc; + entry->write_proc = NULL; + } +} + void register_sn_procfs(void) { register_sn_partition_id(); register_sn_serial_numbers(); register_sn_force_interrupt(); + register_sn_coherence_id(); } #endif /* CONFIG_PROC_FS */ diff --git a/include/asm-ia64/sn/sn_cpuid.h b/include/asm-ia64/sn/sn_cpuid.h index 6f1128f1e895e..529e4f5a497c3 100644 --- a/include/asm-ia64/sn/sn_cpuid.h +++ b/include/asm-ia64/sn/sn_cpuid.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000-2003 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved. */ @@ -93,6 +93,7 @@ */ #define cpu_physical_id_to_nasid(cpi) ((cpi) &0xfff) #define cpu_physical_id_to_slice(cpi) ((cpi>>12) & 3) +#define cpu_physical_id_to_coherence_id(cpi) (cpu_physical_id_to_nasid(cpi) >> 9) #define get_nasid() ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xfff) #define get_slice() ((ia64_getreg(_IA64_REG_CR_LID) >> 28) & 0xf) #define get_node_number(addr) (((unsigned long)(addr)>>38) & 0x7ff) @@ -172,6 +173,11 @@ extern short physical_node_map[]; /* indexed by nasid to get cnode */ #define smp_physical_node_id() (cpuid_to_nasid(smp_processor_id())) +/* + * cpuid_to_coherence_id - convert a cpuid to the coherence domain id it + * resides on + */ +#define cpuid_to_coherence_id(cpuid) cpu_physical_id_to_coherence_id(cpu_physical_id(cpuid)) #endif /* _ASM_IA64_SN_SN_CPUID_H */ -- 2.53.0